Semiconductor Memory Read Disturbance Suppression via Slow Quenching Voltage
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Solution Overview
Problem
Existing memory devices face challenges in suppressing read disturbance, which affects the reliability of read operations and the stability of resistance states in semiconductor memory cells.
Innovation Solution
The implementation of a semiconductor memory device with a variable resistance element and a selecting element in series, where a slow quenching pattern of read voltage is supplied to maintain the specific resistance state during read operations, and read data is generated based on the cell current flowing through the second line, using a first and second read circuit configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional read voltage pattern is supplied to the memory cell, then the read operation can be performed, but read disturbance occurs and the resistance state is not maintained
Solution Approach 1:
The patent applies parameter changes by modifying the voltage waveform characteristics - specifically using a slow quenching pattern with controlled slope and duration instead of conventional fast switching patterns. This changes the temporal parameters of the read voltage to minimize disturbance to the resistance state while still enabling successful read operations.
Solution Approach 2:
The patent implements dynamics by making the read voltage pattern adaptive - the slow quenching pattern dynamically adjusts the voltage transition rates to match the requirements of maintaining resistance states. The voltage waveform is designed with specific rise and fall times that are optimized to prevent read disturbance while enabling reliable detection.
2Speed
If a fast quenching pattern of read voltage is supplied, then the read operation speed is improved, but overshoot in cell current occurs causing read disturbance
Solution Approach 1:
The patent converts the potentially harmful fast voltage transition into a beneficial slow quenching pattern. By deliberately using a slower voltage change rate, the patent eliminates current overshoot and read disturbance while still maintaining acceptable read speeds through optimized waveform timing and duration.
Solution Approach 2:
The patent applies beforehand cushioning by designing the voltage waveform with controlled slopes that prevent excessive current buildup before the measurement phase. The slow quenching pattern acts as a cushion that smooths out current transitions and prevents the harmful overshoot that would otherwise occur with faster switching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses read disturbance, improving the reliability and performance of read operations by maintaining the resistance state and preventing overshoot in cell current, thereby enhancing the overall reliability of the memory device.
Implementation Method 1
semiconductor devices which can store data using a characteristic that they are switched between different resistant states according to an applied voltage or current, for example, an RRAM (resistive random access memory)
Implementation Method 2
a first read circuit suitable for supplying a slow quenching pattern of a read voltage to the first line to generate a cell current, the cell current corresponding to the specific resistance state of the memory cell
Data Source
AI summary
An electronic device includes a semiconductor memory that includes: a memory cell coupled between first and second lines and having a specific resistance state; a first read circuit suitable for supplying a predetermined pattern of a read voltage to the first line to generate a cell current corresponding to the specific resistance state of the memory cell during a read operation mode; and a second read circuit suitable for generating read data based on the cell current flowing through the second line during the read operation mode.