Memory Read ECC Staging for Lower-Power Error Correction
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Solution Overview
Problem
Current memory systems face challenges in reducing current consumption while maintaining efficient data error correction, especially as memory device capacity increases and the likelihood of failed memory cells grows, necessitating improved error correction methods beyond traditional redundancy and error correction circuits.
Innovation Solution
The proposed memory system employs a method where a memory controller transfers read commands and error correction codes in stages, with the first read command detecting errors using a partial error correction code and a second read command accessing a remainder of the code for correction, allowing for efficient error detection and correction while minimizing current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction circuits and redundancy memory cells are used to correct errors in memory devices, then data reliability is improved, but current consumption increases and device complexity increases
Solution Approach 1:
The error correction code is divided into two parts: a first error correction code and a second error correction code. The first ECC is used for initial error detection, and only if errors are detected, the second ECC is used for correction. This segmentation allows the system to avoid full error correction processing in the majority of cases where no errors occur, thereby reducing current consumption while maintaining data reliability.
Solution Approach 2:
The patent applies partial error correction action by using only the first error correction code for error detection in normal operations. Full error correction using both first and second ECCs is applied only when necessary (when errors are detected). This partial action approach reduces unnecessary processing and current consumption while maintaining adequate reliability for the majority of error-free operations.
2Reliability
If traditional error correction circuits and redundancy memory cells are used to correct errors in memory devices, then data reliability is improved, but device complexity increases
Solution Approach 1:
The error correction functionality is segmented into two distinct code components: first error correction code for detection and second error correction code for correction. This segmentation allows the memory controller to implement a simplified two-stage process rather than a complex single-stage full correction system, reducing overall device complexity while maintaining reliability.
Solution Approach 2:
The patent extracts the error correction functionality into a separate memory controller that handles ECC processing externally to the memory device. The memory device itself remains simple, while the controller performs the sophisticated ECC operations. This extraction reduces the complexity burden on the memory device structure while maintaining comprehensive error correction capability.
3Reliability
If all memory chips are activated during read operations, then complete error correction capability is maintained, but current consumption increases
Solution Approach 1:
The memory system is segmented into first memory chips that store data and first ECC, and second memory chips that store second ECC. During normal read operations, only the first memory chips are activated. The second memory chips remain inactive unless error detection triggers a correction operation, thereby reducing current consumption while preserving complete error correction capability when needed.
Solution Approach 2:
The system applies partial activation of memory chips by keeping only the necessary first memory chips active during normal operations. The second memory chips containing the second ECC are activated only partially (i.e., only when error detection occurs). This selective partial activation reduces current consumption while maintaining the ability to perform complete error correction when required.
Data Source
AI summary
An operation method of a memory system including a memory controller and a memory device may include transferring, by the memory controller, a first read command to the memory device; transferring, by the memory device, read data and a part of an error correction code corresponding to the read data to the memory controller in response to the first read command; detecting, by the memory controller, an error of the read data based on the part of the error correction code; transferring, by the memory controller, a second read command to the memory device when the error is detected; transferring, by the memory device, a remainder of the error correction code corresponding to the read data to the memory controller in response to the second read command; and correcting, by the memory controller, the error of the read data based on the remainder of the error correction code.