Memory Read ECC Timing Based on Error Bit Count
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Solution Overview
Problem
Current multiple bits error correcting code (ECC) schemes in non-volatile memory devices are inefficient due to high delay and power consumption, especially when correcting 2-bit or more errors, as such cases are rare, leading to unnecessary full ECC calculations.
Innovation Solution
A data read method that calculates the error bit number and performs corrections only at predetermined timings, returning corrected data immediately if the error bit number is not greater than a predetermined number (e.g., one), and delaying corrections if it is greater, thereby optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full ECC calculation is always performed for reading data, then data reliability is improved, but read time and power consumption increase significantly
Solution Approach 1:
The patent applies partial action by performing ECC calculation only when necessary. Instead of always executing full ECC correction, the system first checks whether error correction is needed and only then performs the calculation, thereby reducing unnecessary computational overhead while maintaining data reliability when errors are present
Solution Approach 2:
The patent implements feedback through a mechanism that determines whether ECC correction is needed based on the data state. The system performs a preliminary check to detect if errors exist, and based on this feedback, decides whether to initiate full ECC calculation, thus avoiding unnecessary operations and reducing read time
2Reliability
If full ECC calculation is always performed for reading data, then data reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by performing ECC calculation only when necessary. Instead of always executing full ECC correction, the system first checks whether error correction is needed and only then performs the calculation, thereby reducing unnecessary computational overhead while maintaining data reliability when errors are present
Solution Approach 2:
The patent implements feedback through a mechanism that determines whether ECC correction is needed based on the data state. The system performs a preliminary check to detect if errors exist, and based on this feedback, decides whether to initiate full ECC calculation, thus avoiding unnecessary operations and reducing power consumption
3Productivity
If ECC correction is delayed for data with high error bits, then system efficiency is improved, but read time variability increases
Solution Approach 1:
The patent applies dynamics by making the ECC correction timing flexible rather than fixed. The system dynamically adjusts when to perform correction based on the error bit count - returning immediately for low error cases and delaying for high error cases - thus optimizing system efficiency while managing read time variability through adaptive scheduling
Data Source
AI summary
A data read method for a memory storage device is provided. The data read method includes: receiving a first read command from a host system for reading first data; calculating an error bit number of the first data; and performing a correction of the first data. If the error bit number is not greater than a predetermined number, finishing the correction of the first data and returning the corrected first data at a pre-defined timing. If the error bit number is greater than a predetermined number, finishing the correction of the first data and returning the corrected first data after the pre-defined timing. In addition, a memory storage device using the data read method is also provided.