Memory Read Circuit With In-Period Error Bit Correction
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Solution Overview
Problem
Current DRAMs with single error correction technology are unable to timely correct multiple error bits, leading to reduced data reliability due to accumulation of errors caused by soft errors from high temperatures or refresh operations.
Innovation Solution
A memory apparatus with a data read-write circuit, parity data read-write circuit, and syndrome operation circuit that corrects error bits during data reading, updates parity data, and writes corrected data back to the memory cell array within the same reading period, enabling instantaneous error correction and improved data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single error correction technology is used, then device complexity is reduced, but data reliability deteriorates due to inability to correct multiple error bits
Solution Approach 1:
The patent performs error checking and correction during the data reading period itself, rather than waiting for a separate correction phase. The syndrome operation circuit generates error decoding signals and the data read-write circuit corrects error bits while data is being read, preventing error accumulation before it occurs. This preliminary action during the reading period resolves the contradiction by maintaining high reliability through timely correction without requiring complex multi-phase operations.
2Speed
If error correction is performed in a separate period, then correction accuracy is improved, but reading speed deteriorates due to additional time required
Solution Approach 1:
The patent merges the error correction operation with the data reading operation by performing both functions during the same reading period. The syndrome operation circuit and data read-write circuit operate concurrently, with the syndrome circuit generating error decoding signals while the data circuit reads and corrects data. This merging eliminates the need for separate correction periods, maintaining high reading speed while ensuring accurate error correction through simultaneous operation of both circuits.
3Reliability
If multiple error bits are allowed to accumulate, then device complexity is reduced, but data reliability deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the syndrome operation circuit continuously monitors data during the reading period, generates error decoding signals based on parity data, and feeds these signals back to the data read-write circuit for immediate correction. This real-time feedback prevents error bit accumulation by detecting and correcting errors as they occur, maintaining high data accuracy while operating efficiently within the same reading period without requiring additional correction cycles.
Data Source
AI summary
In a memory apparatus, a data read-write circuit is configured to access data in a memory cell array. A parity-data read-write circuit is configured to access parity data in a parity memory cell array. A syndrome operation circuit generates an error decoding signal according to the data received from the data read-write circuit and the parity data received from the parity data read-write circuit. During the same read period as reading the data, the data read-write circuit corrects an error bit of the data and outputs the corrected data and a correction bit signal according to the error decoding signal. The syndrome operation circuit further outputs a parity data writing signal to the parity data read-write circuit according to the correction bit signal to update the parity data in the parity memory cell array. The data read-write circuit also writes the corrected data back to the memory cell array.