Memory Read Calibration Using Device-Originated Error Metrics
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Solution Overview
Problem
Existing memory read calibration techniques are inaccurate and latency-prone due to their inability to effectively track and compensate for shifts in threshold voltage distributions caused by factors like charge loss, temperature, and physical defects, leading to uncorrectable read data.
Innovation Solution
Implementing memory device-originated metrics, such as failed byte count and failed bit count, to iteratively adjust read level voltages, minimizing latency and ensuring accuracy by using lookup tables or mathematical transformations to determine optimal read voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional memory read calibration techniques are used, then the read operation can be performed, but the calibration accuracy is insufficient and latency increases due to inability to track voltage threshold shifts
Solution Approach 1:
The patent implements feedback mechanisms by using metrics from previous read operations (such as failed byte count, failed bit count, or bit error rate) to adjust read level voltages in subsequent operations. This closed-loop feedback enables continuous tracking of voltage threshold shifts caused by charge loss, temperature changes, and physical defects, thereby improving calibration accuracy while maintaining operational speed through iterative refinement rather than extensive recalibration
Solution Approach 2:
The patent applies preliminary adjustments to read level voltages based on predicted voltage threshold shifts derived from metrics of previous read operations. By proactively adjusting voltages before actual read errors occur, the system compensates for anticipated drift from charge loss, temperature variations, and program/read disturb effects, thus improving calibration accuracy without waiting for error detection and correction cycles that would increase latency
2Reliability
If read level voltages are adjusted to compensate for voltage threshold shifts, then bit error rate decreases, but the complexity of the calibration process increases
Solution Approach 1:
The patent enables the memory device to self-calibrate by automatically adjusting its own read level voltages based on metrics generated during normal read operations. The device uses its own operational data (failed byte count, failed bit count, bit error rate) to detect voltage threshold shifts and compensate for them without requiring external intervention or complex external calibration equipment, thereby improving reliability while keeping the calibration process integrated and relatively simple
Solution Approach 2:
The patent changes the read level voltage parameters dynamically based on detected voltage threshold shifts. By adjusting voltage levels in response to metrics from previous operations, the system adapts to drift caused by charge loss, temperature changes, and program/read disturb effects. This parameter adjustment approach improves bit error rate while maintaining a relatively simple calibration process that leverages existing operational metrics rather than requiring additional complex measurement and control mechanisms
3Measurement precision
If iterative calibration operations are performed to improve accuracy, then read voltage precision improves, but the number of operations increases causing higher latency
Solution Approach 1:
The patent applies partial calibration adjustments based on metrics from previous read operations rather than performing complete iterative recalibration. By using metrics such as failed byte count, failed bit count, or bit error rate to determine the degree of voltage threshold shift, the system applies just enough correction to achieve acceptable precision without unnecessarily repeating full calibration sequences, thus balancing read voltage precision with operational speed
Data Source
AI summary
Described are systems and methods for memory read calibration based on memory device-originated metrics. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first value of a first metric indicative of a first quantity of data stored in a subset of memory cells associated with at least one non-conducting bitline; determining a first read voltage adjustment value; performing a read operation with respect to the subset of memory cells based on the first read voltage adjustment value; receiving a second value of a second metric indicative of a second quantity of data stored in the subset of memory cells associated with at least one non-conducting bitline; determining a second read voltage adjustment value; and applying the second read voltage adjustment value for reading the plurality of memory cells.