Memory Read Data Path With Parallel Error Recovery
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Solution Overview
Problem
As memory devices increase in density, data bit errors become more likely, leading to incorrect data being returned, which can adversely affect computing device performance, especially in systems utilizing high-density memory like LPDDR5, and existing reliability checks in memory devices often increase latency when errors are detected.
Innovation Solution
Implementing a read data path with a backend data return logic that performs reliability checks before storing data in cache, using metadata to verify data accuracy, and redirecting corrupted data to an LRAID controller for recovery through logical combinations with other data within a RAID stripe, allowing parallel data recovery operations to reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reliability checks are performed in memory devices, then data accuracy is improved, but latency increases when errors are detected
Solution Approach 1:
The patent segments the data path into multiple parallel paths: a first path for data without errors and a second path for data recovery. This segmentation allows the system to handle error-free data and corrupted data simultaneously in parallel, preventing latency accumulation while maintaining reliability checks.
Solution Approach 2:
The patent introduces an intermediary LRAID controller that receives corrupted data from the memory device and performs logical operations to recover correct data. This intermediary component isolates the reliability check function from the main data path, allowing error detection and correction without blocking the primary data flow.
2Quantity of substance
If high-density memory is used, then memory capacity is improved, but data bit errors become more likely
Solution Approach 1:
The patent implements preliminary reliability checks using metadata before data is stored in the cache. This preliminary action detects potential errors in advance, allowing the system to prevent corrupted data from entering the cache while maintaining the benefits of high-density memory.
Solution Approach 2:
The patent uses metadata as a copy of the data that contains reliability information. This metadata copy allows the system to verify data integrity without requiring additional physical memory resources, enabling error detection in high-density memory systems.
3Reliability
If existing reliability checks are implemented, then data accuracy is improved, but bandwidth is reduced
Solution Approach 1:
The patent segments the data handling process into parallel paths that process data simultaneously. The first path handles error-free data directly while the second path handles corrupted data through recovery operations. This segmentation maintains full bandwidth by processing data in parallel rather than sequentially.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining parallel data paths that operate simultaneously. The error detection and correction processes continue in parallel with normal data transfer, preventing bandwidth reduction while maintaining reliability checks throughout the data flow.
Data Source
AI summary
Described apparatuses and methods relate to a read data path for a memory system. A memory system can include logic that receives data from a memory. The data may include first data, parity data, and metadata that enables a reliability check of the data. The logic may perform the reliability check of the data to determine an accuracy of the data. If the data is determined not to include an error, the data may be transmitted for accessing by a requestor. If the data is determined to include an error, however, a data recovery process may be initiated to recover the corrupted data along a separate data path. In doing so, the apparatuses and methods related to a read data path for a memory system and described herein may reduce the likelihood that a memory system returns corrupted data to a requestor.