Memory Read Error Signaling for External Device Verification
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Solution Overview
Problem
Existing information processing apparatuses face challenges in verifying the operation of connected devices like flash memory without modifying the interface circuit, which is typically used for protocol conversion.
Innovation Solution
An information processing apparatus with an error notification generation circuit outside the interface circuit that generates an error response when the system memory outputs data normally, allowing operation verification of the device without altering the interface circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interface circuit is modified to generate error responses for device verification, then operation verification capability is improved, but device complexity and modification requirements increase
Solution Approach 1:
The error response generation function is segmented from the interface circuit and implemented as a separate signal processing circuit. This allows the interface circuit to remain unmodified while the verification functionality is provided by the dedicated signal processing circuit that monitors memory output signals and generates error responses independently.
Solution Approach 2:
The signal processing circuit acts as an intermediary between the memory and the interface circuit. It intercepts the output signals from the memory, determines whether to generate error responses based on verification requirements, and then provides the appropriate signals to the interface circuit, thereby enabling verification without modifying the interface circuit itself.
2Reliability
If the interface circuit is modified to enable error response generation, then device verification is enabled, but ease of manufacture decreases
Solution Approach 1:
By segmenting the error response generation function into a separate signal processing circuit, the interface circuit can be manufactured as a standard component without modifications. The verification functionality is added through the separate circuit module, simplifying the manufacturing process and reducing costs.
3Reliability
If a separate signal processing circuit is added for error notification, then operation verification is enabled, but device complexity increases
Solution Approach 1:
The signal processing circuit is designed with multi-functionality: it monitors memory output signals, determines verification status, generates error responses when needed, and interfaces with the existing interface circuit. This consolidates multiple functions into a single circuit module, minimizing the increase in overall device complexity while enabling comprehensive verification capability.
Data Source
AI summary
An information processing apparatus includes a processor, an interface circuit connectable to a device external to the information processing apparatus, a memory accessible by the processor and accessible by the device via the interface circuit; and a signal processing circuit. The signal processing circuit is disposed in a signal path between the interface circuit and the memory and configured to detect output of data read from the memory even when the interface circuit receives a read request from the device and causes the memory to perform a read operation in response to the read request, and generate an error notification when the memory notifies the signal processing circuit of normal output of the data. The interface circuit is configured to return, to the device, an error response corresponding to the error notification in response to the read request.