Memory Controller Read Error Testing for Bad Block Detection

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Flash memory devices experience read errors due to threshold voltage shifts caused by usage, environmental changes, and manufacturing defects, leading to data loss and increased read delays as existing error handling mechanisms fail to identify and manage bad blocks effectively.

Innovation Solution

A memory test is performed on blocks with read errors to determine if they malfunction, allowing identification of irrecoverable defects and labeling them as bad blocks, preventing further data loss and reducing read delays by avoiding repeat erasing and writing operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error handling mechanisms are repeatedly applied to blocks with read errors, then attempts to recover data are made, but read delays increase and data loss occurs when blocks are actually defective

Engineering Contradiction:
Improvedata storage integrityVSAvoidread delays
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs a memory test on blocks exhibiting read errors to preliminarily determine whether they are defective before attempting data recovery. This preliminary classification prevents time-consuming error handling operations on actually defective blocks, thereby reducing read delays while maintaining data integrity through targeted recovery attempts only on recoverable blocks.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If error handling mechanisms are applied to all blocks with read errors, then potential data recovery is attempted, but system complexity increases due to frequent error handling operations

Engineering Contradiction:
Improvedata recovery capabilityVSAvoiderror handling mechanism frequency
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different handling strategies to different blocks based on their test results: blocks identified as defective are immediately marked and excluded from error handling, while blocks with temporary errors undergo standard error handling procedures. This localized differentiation reduces overall system complexity by avoiding unnecessary error handling operations on defective blocks while maintaining recovery capability for recoverable blocks.

Inventive Principle:
Principle #3Local quality

3Loss of time

If blocks with read errors are immediately marked as bad blocks, then read delays are reduced by avoiding further operations, but false positives occur when blocks could actually be recovered

Engineering Contradiction:
Improveread delaysVSAvoiddata loss
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent performs a memory test as a preliminary action before marking blocks as bad, allowing differentiation between permanently defective blocks and those with temporary errors. Blocks that fail the memory test are confidently marked as bad to prevent future read delays, while blocks passing the test continue to undergo error handling, thus avoiding false positives and potential data loss while maintaining fast read performance.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12148493B2Memory controller with read error handling
Publication Date: 2024.11.19 YANGTZE MEMORY TECH CO LTD
  • US12148493B2 patent drawing
  • US12148493B2 patent drawing
  • US12148493B2 patent drawing

AI summary

A method for handling a read error on a block of a memory device is disclosed. In response to a read failure indicating that at least one error handling mechanism has handled the read error on the block and fails to read data stored in the block, a memory test is trigged to be performed on the block. The memory test is configured to determine whether the block malfunctions.