Semiconductor Memory Read Pipeline Using Sense-Amplifier Latches
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in improving data reading rates, particularly in efficiently managing and transferring data within the memory system.
Innovation Solution
The semiconductor storage device incorporates a memory string with a bit line, sense amplifier including first and second latch circuits, a cache memory with a third latch circuit, and a control circuit that performs sequential read operations in response to command sets, allowing for improved data transfer and storage efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional read operations are used in semiconductor storage devices, then data reading can be performed, but the data reading rate is limited and operational latency is high
Solution Approach 1:
The patent implements preliminary action by performing a first read operation to pre-fetch data into the sense amplifier latch circuit before it is actually needed. When a second read command arrives, the data is already available in the latch circuit, allowing immediate transfer to the cache memory without waiting for the memory string read operation to complete. This pre-fetching mechanism reduces operational latency and improves data reading rate by preparing data in advance.
2Reliability
If data is transferred through multiple latch circuits sequentially, then data storage and transfer are reliable, but the transfer time increases
Solution Approach 1:
The patent applies continuity of useful action by enabling overlapping execution of read operations and data transfers. While the first read operation is in progress, the controller can issue a second read command, and the data from the first operation is continuously transferred to the cache memory without idle waiting periods. This continuous pipeline operation maintains data transfer reliability through proper latch circuit sequencing while minimizing transfer time by eliminating gaps between operations.
Data Source
AI summary
A semiconductor storage device includes a memory string, a sense amplifier including first and second latch circuits, a cache memory including a third latch circuit, and a control circuit. The control circuit is configured to perform a first read operation in response to a first command set and consecutively perform a second read operation in response to a second command set received during the first read operation. During the first read operation, data read from the memory string is stored in the first latch circuit. When the second command set is received at a first timing, the control circuit transfers the data to the second latch circuit, and then to the third latch circuit. When the second command set is received at a second timing before the first timing, the control circuit directly transfers the data to the third latch circuit.