Memory Read Latency Control via Charge Pump Voltage Maintenance
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Solution Overview
Problem
Existing memory systems face challenges in reducing the latency between consecutive read operations due to the setup time required for charge pumps and sense amplifiers, which limits the speed of memory access.
Innovation Solution
The solution involves maintaining the charge pump output voltage at the word line operation voltage from the completion of a first operation command to the initiation of a second command, thereby eliminating the need for a setup period for the charge pump and word line voltage, allowing for reduced read latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the charge pump and sense amplifier are allowed to complete their setup time between operations, then the reliability of memory operations is maintained, but the latency between consecutive read operations increases
Solution Approach 1:
The charge pump is activated in advance before the read command is issued, so that by the time the read operation begins, the charge pump has already completed its setup and is ready to provide the necessary voltage. This preliminary activation eliminates the setup time that would otherwise occur during the critical path of the read operation, thereby reducing latency while maintaining reliable operations
Solution Approach 2:
The charge pump remains active continuously across multiple consecutive read operations rather than being deactivated and reactivated between operations. This continuous operation eliminates repeated setup times and allows the system to maintain the charge pump output voltage throughout the sequence of reads, significantly reducing the latency between consecutive operations
2Loss of time
If the charge pump speed is increased to reduce setup time, then the latency between operations decreases, but the complexity and power consumption of the charge pump increases
Solution Approach 1:
Instead of increasing the charge pump speed, the invention activates the charge pump in advance before the read command. This allows the use of a standard-speed charge pump while still achieving reduced latency, avoiding the need for complex high-speed charge pump designs
Solution Approach 2:
The charge pump activation is made dynamic and conditional based on the timing requirements of consecutive read operations. The control circuitry determines when to activate the charge pump in advance based on the expected timing of the next read operation, optimizing performance without requiring a permanently high-speed charge pump
3Loss of time
If the charge pump output voltage is maintained at word line operation voltage between operations, then the read latency is reduced, but the power consumption increases
Solution Approach 1:
The charge pump is activated in advance only when a sequence of consecutive read operations is detected or anticipated. This conditional preliminary activation ensures that the charge pump maintains voltage only when necessary for performance optimization, avoiding unnecessary power consumption during idle periods or when reads are not consecutive
Solution Approach 2:
The charge pump operation mode is dynamically adjusted based on the timing characteristics of read operations. When reads are consecutive and timing is critical, the charge pump remains active with output maintained. When reads are spaced out, the charge pump is deactivated to conserve power, achieving adaptive optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces read latency by eliminating the charge pump and word line setup periods, enhancing the speed of consecutive read operations in memory systems, particularly beneficial for NAND type memory where continuous read operations are common.
Implementation Method 1
a charge pump with a charge pump output coupled to the memory array
Data Source
AI summary
An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.