Memory Controller Read-Level Switching for Faster Error Recovery
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Solution Overview
Problem
Current memory systems experience increased latency during data read and decoding operations due to suboptimal read levels, which can lead to prolonged processing times and uncorrectable errors, especially in high program and erase cycles and long data retention scenarios.
Innovation Solution
A memory system and method that utilize a controller to perform read operations on select blocks using a sequence of read levels, determining whether to stop decoding at each level based on syndrome values, and transitioning to the next read level if decoding fails, thereby reducing latency and improving error recovery efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the read operation continues at the select read level until maximum iterations are completed, then decoding thoroughness is improved, but latency is increased
Solution Approach 1:
The patent uses syndrome values as feedback to monitor decoding progress and determine when to switch read levels. The syndrome value indicates whether errors are being corrected, and this feedback drives the dynamic decision to continue or switch read levels, resolving the contradiction between thoroughness and latency.
Solution Approach 2:
The patent dynamically adjusts the read level based on syndrome value feedback rather than statically completing all iterations at each level. This dynamic approach allows the system to adaptively switch read levels when decoding stagnates, reducing latency while maintaining decoding thoroughness.
2Reliability
If multiple read levels are used for error recovery, then error correction capability is improved, but device complexity is increased
Solution Approach 1:
The patent segments the error recovery process into multiple read levels, each targeting different error conditions. This segmentation allows the controller to systematically try different read levels based on syndrome feedback, improving error correction capability while managing complexity through structured segmentation.
Solution Approach 2:
The patent changes the read level parameter dynamically during the read operation based on syndrome values. By adjusting this key parameter (read level) rather than changing the entire decoding architecture, the system improves error correction capability with minimal increase in controller complexity.
3Loss of time
If the controller switches to the next read level before maximum iterations, then latency is reduced, but decoding accuracy may be compromised
Solution Approach 1:
The syndrome value serves as feedback to determine when switching read levels is appropriate. The feedback mechanism ensures that switching occurs only when further iterations at the current level are unlikely to improve decoding accuracy, thus reducing latency without compromising decoding accuracy.
Solution Approach 2:
The patent performs preliminary assessment using syndrome values to determine whether continuing iterations at the current read level is worthwhile. This preliminary action prevents wasteful iterations that would increase latency without improving accuracy, allowing early switching when decoding has stagnated.
Data Source
AI summary
A memory controller performs an error recovery operation. The controller performs a read operation on a select block using a select read level; decodes data associated with the read operation to generate a syndrome value; determines whether to stop, before a maximum number of iterations, the read operation and the decoding at the select read level, using the syndrome value; when it is determined to stop the read operation and the decoding at the select read level, selects a next read level in a sequence of read levels; and uses the next read level for a subsequent read operation.