Non-volatile Memory Read Lockout Control for Power Efficiency
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Solution Overview
Problem
Non-volatile memory devices face high power consumption during sensing operations due to massively parallel sensing methods, which is inefficient and wasteful, especially with constant voltage bit line schemes requiring precharge operations.
Innovation Solution
Implementing a method that provides multiple series of demarcation threshold voltages to identify and lock out high conduction current memory cells during subsequent sensing operations, reducing the number of cells that need to be sensed by selectively grounding bit lines and inhibiting conduction currents, thereby conserving power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If massively parallel sensing is used to improve read and program performance, then productivity is improved, but power consumption increases
Solution Approach 1:
The patent segments the sensing operation into multiple passes (first pass, second pass, third pass) with different demarcation voltages. In each pass, only specific memory cells within certain voltage ranges are sensed, rather than sensing all memory cells in parallel simultaneously. This segmentation reduces the number of cells actively sensed in each operation, thereby reducing power consumption while still achieving complete read/verify functionality across all memory states.
Solution Approach 2:
The patent applies preliminary locking out action before sensing in subsequent passes. Memory cells that were identified in previous passes are locked out (inhibited) before the next sensing operation begins. This preliminary action prevents these cells from consuming power during sensing operations where they would not contribute to new information gathering, thus reducing overall power consumption while maintaining reading accuracy.
2Measurement precision
If constant voltage bit line schemes are used with precharge operation, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent applies partial action by performing precharge operations only on bit lines associated with memory cells that are actually being sensed in the current pass, rather than precharging all bit lines. Memory cells are divided into different voltage range groups, and only the relevant groups require precharge in each pass. This partial precharging maintains measurement precision for the cells being sensed while avoiding unnecessary power consumption on other bit lines.
Solution Approach 2:
The patent segments the bit line precharging operation into multiple groups corresponding to different memory cell voltage ranges. In each sensing pass, only specific bit line groups requiring precharge are activated, rather than all bit lines being precharged simultaneously. This segmentation approach maintains the constant voltage bit line scheme's measurement precision while significantly reducing the number of active bit lines and associated power consumption in each pass.
Data Source
AI summary
Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.