Memory Read Circuit Using Multi-Bit ECC for Programmed-Error Bits
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Solution Overview
Problem
Conventional memory systems require additional hardware for column repair units to correct programmed errors, increasing hardware costs and reducing available memory capacity due to the limitations of single-bit error correction codes.
Innovation Solution
A data processing circuit and method utilizing multi-bit error correction codes, including a page buffer, syndrome calculators, a key equation device, Chien searcher, address counter, latch, switching device, and correcting unit to reduce the number of column repair units by correcting programmed-error bits using syndrome polynomials and reference codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If column repair units are added to address programmed-error memory cells, then data integrity is improved, but hardware cost increases
Solution Approach 1:
The patent replaces the mechanical hardware-based column repair units with a software-based error correction method using multi-bit error correction codes. The correcting unit uses syndrome calculators and reference codes to detect and correct programmed errors in memory cells, eliminating the need for physical repair hardware while maintaining data integrity.
Solution Approach 2:
The patent changes the error correction capability parameter from single-bit to multi-bit error correction. By implementing error correction codes that can handle multiple-bit errors simultaneously, the system reduces the number of repair units needed while improving the ability to correct programmed errors, thus lowering hardware cost while maintaining reliability.
2Reliability
If column repair units are added to address programmed-error memory cells, then error correction capability is improved, but available memory capacity decreases
Solution Approach 1:
The patent replaces physical repair units with a software-based correction system that operates on existing memory cells. This substitution eliminates the need to dedicate separate hardware resources for repair, thereby preserving available memory capacity while maintaining error correction capability through multi-bit error correction codes.
3Device complexity
If single-bit error correction codes are used, then hardware cost is reduced, but error correction capability is insufficient for programmed errors
Solution Approach 1:
The patent changes the error correction parameter from single-bit to multi-bit capability by implementing error correction codes designed to handle multiple simultaneous errors. This parameter change allows the system to correct programmed errors that affect multiple bits while using cost-effective hardware resources, resolving the contradiction between hardware cost and error correction capability.
Data Source
AI summary
A data processing method is provided. Target page data are read from a memory cell array and addresses of multiple programmed-error bits are stored. A first syndrome polynomial and a second syndrome polynomial are obtained according to the target page data, and the target page data are saved as a first codeword and a second codeword. An errata locator polynomial is obtained according to the syndrome polynomials, and a first error count and a second error count are obtained according to the errata locator polynomial, the first codeword and the second codeword. A set of reference codes is obtained according to the errata locator polynomial. Read page data are outputted according to the addresses of the programmed-error bits, the first error count and the second error count. The read page data are corrected according to the set of reference codes to obtain corrected read page data.