Memory Chip Read Circuit With Variable Resistors for Noise Isolation
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Solution Overview
Problem
Memory chips, such as DRAM chips, generate noise during reading operations due to signal interference from capacitors in neighboring chips, degrading data quality.
Innovation Solution
A memory device with variable resistors and capacitors coupled in series, where the processor adjusts the resistance of these components to minimize signal interference by isolating chips during reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If the processor performs reading operations to memory chips, then data can be read from memory, but noise is generated due to signal interference from capacitors in neighboring chips
Solution Approach 1:
A variable resistor is introduced as an intermediary component between the capacitor and the memory chip. This variable resistor acts as a mediator that can be dynamically adjusted to control signal interference. When reading operations are performed, the variable resistor's resistance is increased to block noise signals from propagating through the capacitor to neighboring chips, thereby reducing noise interference while allowing data transmission when needed.
Solution Approach 2:
The system employs a dynamically adjustable variable resistor rather than a fixed resistor. The resistance value is changed based on the operational state: during reading operations, the resistance is increased to minimize noise interference; during writing operations or idle states, the resistance is decreased to maintain proper signal transmission. This dynamic adjustment resolves the contradiction between data quality and noise generation.
2Loss of information
If variable resistors are added to reduce noise interference, then data signal quality improves, but device complexity increases
Solution Approach 1:
The invention changes the resistance parameter of the variable resistor based on operational requirements. By adjusting the resistance value between high (for noise reduction during reading) and low (for signal transmission during writing), the system achieves improved signal quality without requiring fundamentally different circuit architectures. This parameter-based control adds minimal complexity compared to redesigning the entire memory interface circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances data signal quality by reducing noise interference, ensuring clear and accurate data transmission.
Implementation Method 1
The first variable resistor is coupled in series with the first capacitor. The second variable resistor is coupled in series with the second capacitor. The processor is configured to increase a resistance of the first variable resistor in response to reading the first data via the first node, and configured to increase a resistance of the second variable resistor in response to reading the second data via the second node.
Data Source
AI summary
A memory device includes a first chip, a second chip and a processor. The second chip is coupled to the first chip at a first node. The second chip includes a first capacitor and a first variable resistor. The first capacitor is coupled to the first node. The first variable resistor is coupled in series with the first capacitor. The processor is coupled to the first node, and is configured to perform a first read operation to the first chip via the first node. A method for operating a memory device is also disclosed herein.