Semiconductor Memory Read Control Circuit Noise Reduction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in reducing read time, particularly in NAND flash memories, where existing read modes either suffer from high noise coupling or slower operation speeds due to the need for multiple read voltage levels.
Innovation Solution
The implementation of a semiconductor memory device with a control circuit that selectively executes either an all-bit-line read operation or a shielded bit-line read operation based on the number of read voltage levels required, optimizing the read process to minimize noise and enhance speed by applying shielding voltages to non-target bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If shielded bit-line read operation is used to reduce coupling noise, then noise immunity is improved, but read time increases due to sequential reading of bit line groups
Solution Approach 1:
The patent dynamically switches between ABL and SBL read modes based on the number of read voltage levels required. When only one or two voltage levels are needed, ABL mode is used for fast parallel reading. When three or more voltage levels are required, SBL mode is used to reduce coupling noise. This dynamic adaptation resolves the contradiction by selecting the optimal mode for each specific read operation.
Solution Approach 2:
The patent changes the operational parameters of the bit lines by applying different voltage configurations. In ABL mode, all bit lines are read simultaneously with standard voltage levels. In SBL mode, bit lines are divided into groups with different voltage levels applied sequentially, and shield voltages are applied to non-target bit lines during reading. This parameter change enables noise reduction while managing read time through selective application.
2Speed
If all-bit-line read operation is used to read data from all bit lines simultaneously, then read speed is improved, but coupling noise between bit lines increases
Solution Approach 1:
The patent changes the voltage parameters applied to bit lines based on the reading mode. In ABL mode, all bit lines receive the same voltage level simultaneously enabling fast reading. In SBL mode, different voltage levels are applied to different bit line groups sequentially, and shield voltages are applied to non-target bit lines. This parameter adaptation allows the system to achieve fast reading when noise is not critical while reducing noise when multiple voltage levels are required.
Solution Approach 2:
The patent dynamically selects between ABL and SBL modes based on the number of read voltage levels required. When the data requires three or more voltage levels for accurate reading, the system switches to SBL mode to reduce coupling noise. When fewer voltage levels are needed, ABL mode is used for maximum speed. This dynamic selection resolves the contradiction between speed and noise.
3Measurement precision
If multiple read voltage levels are applied to determine data in memory cells, then measurement precision is improved, but read time increases due to sequential operations
Solution Approach 1:
The patent dynamically adapts the read operation mode based on the number of voltage levels required for accurate data determination. When three or more voltage levels are needed for precise measurement, SBL mode is used to prevent coupling noise that would compromise accuracy. When fewer voltage levels suffice, ABL mode is used for faster reading. This dynamic adaptation maintains measurement precision while minimizing read time.
Solution Approach 2:
The patent changes the voltage application parameters based on the reading mode selected. In SBL mode, multiple voltage levels are applied sequentially to different bit line groups with shield voltages applied to non-target lines, ensuring accurate data determination without noise interference. In ABL mode, voltage levels are applied simultaneously to all bit lines for faster but potentially noisier reading. This parameter flexibility allows the system to optimize both precision and speed.
Data Source
AI summary
A memory device includes a memory cell array with memory strings including a first and second select transistor and memory cells between the first and second select transistors. Each memory string has a bit line connected thereto. A different word line is connected to each of the memory cells of a memory strings. A control circuit is configured to execute a first read operation in which data is read at the same time from memory cells connected to all the bit lines and a second read operation in which data is read from memory cells connected to a first subset of bit lines and a shield voltage is applied to a second subset of bit lines in the plurality of bit lines. The controller selects the first or second read operation for execution according to the number of read voltage levels required for determining data in the memory cells.