Semiconductor Memory Device High-Speed Read Noise Reduction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in simultaneously reading data from all cells in a row direction at high speed while suppressing noise, especially in multi-value memory systems, due to limitations in threshold voltage settings and bit line operations.
Innovation Solution
A semiconductor memory device design that includes a memory cell array with multiple bit lines and source lines connected to the sources of memory cells during read operations, allowing for simultaneous data read from all cells by neutralizing charge on bit lines with sub-source lines, enabling stable and high-speed data access across all cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a bias voltage is applied to the source and well to read negative threshold voltage, then read capability is improved, but source noise increases and current flows excessively to the power supply circuit
Solution Approach 1:
The bit line is divided into two separate lines: a first bit line for reading positive threshold voltages and a second bit line for reading negative threshold voltages. This segmentation allows independent control and charge management for each bit line, preventing charge interference and noise that would occur in a shared bit line configuration.
Solution Approach 2:
A charge pump circuit acts as an intermediary to generate the negative voltage for the second bit line. This mediator component enables the system to achieve negative voltage operation without directly applying bias to the source and well, thereby avoiding the harmful effects of excessive current and noise while still enabling negative threshold voltage reading capability.
2Device complexity
If multiple bit lines share a common source line, then device complexity is reduced, but read speed decreases due to charge neutralization requirements
Solution Approach 1:
The source line is segmented into multiple independent source lines, with each source line dedicated to a specific bit line. This segmentation eliminates the need for charge neutralization between bit lines that would occur with a shared source line, enabling simultaneous high-speed reading from multiple bit lines without interference.
Solution Approach 2:
Charge is pre-loaded onto the bit lines before the read operation begins. By having charge already available on the bit lines and independent source lines, the system can immediately perform read operations at high speed without waiting for charge neutralization or redistribution that would be required in a shared source line configuration.
3Quantity of substance
If threshold voltage distribution is narrowed to store more bits per cell, then memory capacity increases, but write speed decreases
Solution Approach 1:
The threshold voltage range is segmented into distinct positive and negative regions, with separate bit lines dedicated to each region. This segmentation allows independent programming operations on different threshold voltage ranges, enabling faster write operations by avoiding the need to sequentially program through narrow threshold distributions while still achieving high memory capacity through multi-level cell technology.
Data Source
AI summary
A plurality of memory cells are arranged in a memory cell array. The plurality of memory cells are connected to a plurality of word lines and a plurality of bit lines. A plurality of source lines are disposed along the plurality of bit lines. The plurality of source lines are connected respectively to sources of the plurality of memory cells at a time of data read.