Memory Cell Read Offset Calibration Using Voltage Relationships
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Solution Overview
Problem
Memory cell read voltage levels drift over time due to environmental conditions and usage, leading to inaccurate baseline read voltages and increased bit error rates, especially after initial calibration procedures.
Innovation Solution
A calibration procedure using a relationship between read voltage levels and voltage offsets to estimate updated voltage offsets and corresponding read voltage levels, potentially linear or non-linear, to adjust the read voltage levels and reduce bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If baseline read voltage levels are used for memory cells, then the reading process is simple and fast, but the read voltage levels drift over time due to environmental conditions and usage, leading to inaccurate readings and increased bit error rates
Solution Approach 1:
The patent applies preliminary action by performing calibration procedures before normal operation to establish accurate read voltage levels. The system performs initial calibration to determine baseline read offsets, then uses these pre-determined values during subsequent read operations to maintain accuracy without requiring continuous complex calibration during use.
Solution Approach 2:
The patent implements feedback mechanisms where the system monitors read operations and compares actual read results against expected values. When drift is detected or errors occur, the system uses this feedback information to adjust or re-calibrate read voltage levels, creating a closed-loop system that maintains accuracy while managing complexity through intelligent monitoring and adjustment.
2Measurement precision
If calibration procedures are performed to adjust read voltage levels, then reading accuracy is improved, but the calibration process itself may fail to accurately determine updated voltage offsets, especially after initial calibration
Solution Approach 1:
The patent segments the calibration process into multiple distinct phases: initial calibration to establish baseline read offsets, intermediate verification through sample read operations, and final adjustment based on measured errors. This segmentation allows each phase to be optimized independently, improving overall precision while identifying where reliability issues may occur and how to address them.
Solution Approach 2:
The patent uses copying by creating reference copies of known voltage levels and threshold values during calibration. The system reads known test patterns at different voltage levels and uses these copied reference values to determine accurate offset corrections, allowing precise measurement without directly measuring the entire voltage range, thereby improving both precision and reliability.
3Quantity of substance
If multiple read voltage levels are used for multi-level memory cells, then storage density is increased, but the complexity of determining accurate read offsets for each level increases
Solution Approach 1:
The patent segments the read offset determination into separate calibration processes for each memory cell level. Each level receives dedicated calibration that determines its specific read offset independently, allowing the system to handle multiple levels with the same systematic approach without proportionally increasing overall complexity. The segmentation enables parallel processing of different levels during calibration.
Solution Approach 2:
The patent applies parameter changes by adjusting read voltage levels and offset values specifically for each memory cell level based on its characteristics. Rather than using a single universal calibration, the system modifies calibration parameters (voltage thresholds, offset values) to match the specific requirements of each level, enabling high storage density while managing complexity through level-specific parameter optimization.
Data Source
AI summary
Methods, systems, and devices for techniques for determining memory cell read offsets are described to support determining voltage offsets and corresponding read voltage levels for one or more memory cell levels using a relationship between read voltage levels and voltage offsets. A memory device may estimate first voltage offsets using a first procedure and may perform a read operation using the first voltage offsets. If a first voltage offset results in a read error for a corresponding memory cell level, the memory device may determine an updated voltage offset using the relationship. The relationship may predict a voltage offset for a given read voltage level, such that the memory device may use the relationship to predict an updated voltage offset for a memory cell level. The memory device may use the updated voltage offset(s) to perform a second read operation for the one or more memory cells.