Semiconductor Memory Device Internal Read-Operate-Write Atomicity
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Solution Overview
Problem
In shared-memory multi-core systems, ensuring atomicity during read-operate-write operations is challenging due to the need for multiple memory accesses, which complicates synchronization between cores or threads.
Innovation Solution
A semiconductor memory device with a memory cell array, read and write circuits, and an operation unit that can perform operations on data internally, allowing read-operate-write operations to be executed in a single memory access by using modified read and write modes, where operation assignment information is applied through address lines to perform arithmetic and logical operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read-operate-write operations are performed using traditional separate read and write commands, then atomicity can be ensured through multiple memory accesses, but memory access time increases and synchronization complexity increases
Solution Approach 1:
The patent combines read, write, and operation functions into a single memory access operation. The memory device internally performs read-operate-write sequences by receiving one command that triggers both reading data from memory cells, performing operations on that data, and writing results back, all within a single access cycle. This merging eliminates the need for separate read and write commands while maintaining atomicity through internal control logic that manages the entire sequence atomically.
Solution Approach 2:
The memory device is designed with multi-functional capability to perform not only traditional read and write operations but also arithmetic and logical operations directly within the memory array. The operation unit integrated in the memory device can execute various operations (ADD, SUB, AND, OR, etc.) on data retrieved from memory cells, making the memory device a universal component that handles both storage and processing functions, thereby reducing the need for separate processor interventions and multiple memory accesses.
2Reliability
If read-operate-write operations are performed using traditional separate read and write commands, then operation correctness can be verified through multiple accesses, but device complexity increases
Solution Approach 1:
The patent merges multiple separate operations (read, operation, write) into a single integrated memory access command. The control circuit within the memory device manages the entire read-operate-write sequence internally, receiving a single command that specifies the operation type and memory address. This integration reduces synchronization complexity by eliminating the need for coordinated multiple accesses between processor and memory, as the entire sequence is handled atomically within the memory device itself.
Solution Approach 2:
The memory device performs self-service by internally executing operations on data retrieved from its own memory cells without requiring external processor intervention for each operation step. The operation unit within the memory device autonomously performs arithmetic and logical operations on the read data, and the control circuit automatically manages the write-back of results, reducing the overall system complexity and synchronization requirements.
Data Source
AI summary
A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on read data obtained by the read circuit according to operation assignment information applied through an address line to reduce memory access time when entering a modified read mode. In addition, the semiconductor memory device may optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode.