Memory IC Read Output Control Without DLL Domain Crossing
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Solution Overview
Problem
Current semiconductor IC devices face complexity and large layout area requirements when modifying circuit structures to quickly produce data in response to an external read command, particularly due to the need for complex control of DLL clock signals for synchronizing data with CAS latency and external clock signals.
Innovation Solution
A semiconductor IC device and method that utilize a core strobe signal generator to latch read command signals according to an internal clock signal, generating control signals to output data stored in a memory cell in a predetermined order, including a data output unit with a pipe latch and data selector, and a read controller that uses both the core strobe signal and internal clock signal to produce control signals for fast data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a DLL clock signal is used to synchronize data with CAS latency and external clock signal, then data synchronization is improved, but device complexity and layout area increase due to the need for domain crossing block and read controller
Solution Approach 1:
The patent extracts the essential function of data synchronization from the complex DLL-based domain crossing system and implements it directly in the read controller using the internal clock signal. This removes the need for separate domain crossing block and complex DLL control logic, simplifying the overall circuit structure while maintaining data synchronization capability.
Solution Approach 2:
The read controller is designed to perform multiple functions: it directly generates control signals for the pipe latch and data selector using the internal clock signal, and also handles data synchronization. This multi-functional approach eliminates the need for separate domain crossing block and reduces overall device complexity.
2Loss of time
If DLL clock signal and domain crossing block are used to control pipe latch and data selector, then data output timing is improved, but layout area occupation increases
Solution Approach 1:
The patent merges the functions of the domain crossing block and read controller into a single integrated read controller that operates using the internal clock signal. This consolidation reduces the layout area occupation while maintaining the ability to control pipe latch and data selector for timely data output.
3Productivity
If complex circuit modifications are made to meet data output requirements, then data output speed is improved, but device complexity and layout area increase
Solution Approach 1:
Instead of using the conventional approach of generating control signals based on DLL clock signal from external clock, the patent inverts the approach by generating control signals directly from the internal clock signal within the internal clock domain. This reversal simplifies the circuit structure while achieving fast data output.
4Reliability
If DLL clock signal is used for read controller operation, then external clock synchronization is improved, but internal clock domain coordination becomes complex
Solution Approach 1:
The patent uses the internal clock signal as an intermediary to coordinate between the internal clock domain and external clock domain. The read controller generates control signals based on the internal clock signal, which naturally synchronizes with the external clock through the existing clock generation architecture, simplifying clock domain coordination.
Data Source
AI summary
A semiconductor IC device includes a core strobe signal generator configured to latch a read command signal according to an internal clock signal to generate a core strobe signal, a core block configured to output data stored in a memory cell in response to the core strobe signal, a data output unit configured to latch data output from the core block according to a plurality of control signals and output the latched data in a predetermined order, and a controller configured to generate the plurality of control signals by using both the core strobe signal and the internal clock signal.