Nonvolatile Memory Multi-Plane Read Current Peak Reduction
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Solution Overview
Problem
The increasing number of vertically stacked word lines in flash memory devices leads to a current peak during read operations, which degrades read speed and is challenging to manage with existing technologies, particularly in Cell Over Peri (COP) structures where the peripheral area for charge pumps is limited.
Innovation Solution
A nonvolatile memory device with a multi-plane structure that employs a pseudo plane independent read mode, where the setup times of word line voltages are sequentially delayed for each plane, reducing the current peak without altering the charge pump structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of vertically stacked word lines is increased, then the storage capacity is improved, but the current peak during read operation increases
Solution Approach 1:
The patent divides the word line setup operation into separate segments for each plane. Instead of simultaneously setting up all word lines across multiple planes, the control circuit sequentially sets up word lines plane by plane, with each plane's word line setup occurring at different time intervals. This segmentation of the setup operation reduces the concurrent current demand and eliminates the current peak that would occur with simultaneous setup of all word lines.
2Object-generated harmful factors
If the word line setup time is reduced to cope with increasing current peak, then the read speed is degraded
Solution Approach 1:
The control circuit performs preliminary sequencing of the word line setup operations. By pre-determining the sequential order in which planes will have their word lines set up, the system can manage current peaks without compromising read speed. The preliminary arrangement ensures that high current draw periods are minimized while maintaining efficient read operation timing.
3Device complexity
If the peripheral area for charge pump is increased, then the charge pump load is reduced, but the device area is increased
Solution Approach 1:
The patent introduces dynamic timing control for the charge pump operations. Instead of requiring a larger static charge pump area to handle all word lines simultaneously, the control circuit dynamically sequences the charge pump activation across different planes. This dynamic approach allows the same charge pump area to service more word lines by time-division, reducing the need for increased peripheral area while managing the charge pump load effectively.
Data Source
AI summary
A nonvolatile memory device includes a cell array divided into a plurality of planes, a voltage generator configured to generate a word line voltage applied to word lines of each of the plurality of planes, a row decoder configured to transmit the word line voltage to the cell array in response to an address, and a control circuit configured to set up voltages of word lines of each of the plurality of planes to the word line voltage in response to an activated pseudo plane independent read mode setting. The control circuit is configured to sequentially shift voltage setup times of the word lines by a specified time delay corresponding to a number of the plurality of planes.