Semiconductor Memory Read Process Using Ramp Voltage Waveform
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in accurately and efficiently determining data stored in memory cells due to variations in word-line voltage arrival times across memory cells, leading to increased read process time and reduced accuracy, especially as the number of bits per memory cell increases.
Innovation Solution
A semiconductor memory device employs a word-line voltage waveform with a period of increasing and decreasing voltage values, allowing sense amplifiers to measure the duration of a target period to accurately determine the threshold voltage of memory cells, independent of voltage arrival time delays, thereby enhancing read speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional read methods are used to determine data in memory cells, then the read process can be performed, but variations in word-line voltage arrival times across memory cells cause reduced accuracy and increased read process time
Solution Approach 1:
The patent applies periodic action by using a ramp voltage waveform that continuously increases over time, allowing the system to capture the transition point of each memory cell as it occurs naturally during the voltage sweep. This periodic scanning approach enables accurate threshold voltage measurement for each cell without requiring synchronization across multiple cells, thereby maintaining high measurement precision while reducing overall read time.
Solution Approach 2:
The patent implements preliminary action by pre-charging bit lines and source lines to specific voltage levels before applying the ramp voltage to the word line. This preliminary preparation ensures that when the ramp voltage reaches each memory cell, the cell is already in the correct initial state for accurate threshold voltage detection, eliminating the need for repeated measurements and reducing read process time.
2Quantity of substance
If the number of bits per memory cell is increased to improve storage capacity, then more data can be stored, but variations in voltage arrival times cause greater measurement errors and reduced read accuracy
Solution Approach 1:
For multi-bit memory cells, the patent uses a continuous ramp voltage waveform that systematically sweeps through all threshold voltage ranges. This periodic scanning allows each memory cell's multiple threshold voltage levels to be detected in sequence as the ramp voltage passes through them, enabling accurate multi-bit reading without the synchronization problems that would arise with stepped voltage approaches.
Solution Approach 2:
The patent changes the voltage parameter continuously over time using a ramp waveform rather than applying fixed voltage steps. This continuous parameter change allows the system to capture the natural transition behavior of multi-bit memory cells, where multiple threshold voltages are encountered in sequence during the ramp, thereby maintaining high measurement precision even as storage capacity increases.
3Productivity
If multiple memory cells are read simultaneously to improve productivity, then read speed increases, but variations in word-line voltage arrival times across cells cause measurement errors
Solution Approach 1:
The patent enables simultaneous reading of multiple memory cells by applying a single ramp voltage waveform to all cells on a word line. Each cell's threshold voltage is detected independently as the ramp voltage passes through its specific threshold level, with the periodic nature of the ramp ensuring that all cells are evaluated on the same time basis, eliminating synchronization errors while maintaining high read speed.
Solution Approach 2:
The patent performs preliminary actions by pre-configuring the read circuitry and pre-charging all bit lines and source lines simultaneously before applying the ramp voltage. This preliminary preparation ensures that when the ramp voltage is applied to multiple cells simultaneously, all cells are in the correct initial state, enabling accurate simultaneous measurement without cross-interference.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.