Memory Cell Read Voltage Selection Using Toggled Reference Patterns
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Solution Overview
Problem
Existing memory devices face challenges in accurately determining read voltages due to resistance drift in resistance variable memory cells, leading to errors and increased read operation time, especially when using known patterns that do not account for varying threshold voltage distributions and wear disparities between pattern and data cells.
Innovation Solution
Implementing a memory device that toggles or swaps known reference patterns between SET and RESET states for each ERASE and PROGRAM command, ensuring pattern cells mirror data cell behavior by maintaining similar wear and drift, allowing for quicker and more accurate determination of initial read voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If known reference patterns are used for reading memory cells, then read operations can be performed, but resistance drift in pattern cells causes inaccurate read voltage determination and increased read operation time
Solution Approach 1:
The patent applies dynamics by making the reference pattern configurable and adaptable rather than static. The controller can toggle between different known patterns (e.g., all-ones, all-zeros, or custom patterns) based on the actual data pattern being read. This dynamic adaptation allows the system to select the most appropriate reference pattern for each read operation, improving measurement precision while reducing the time needed to compensate for resistance drift.
Solution Approach 2:
The patent changes the parameter of the reference pattern itself by allowing it to be configured in different states (patterns) rather than using a single fixed pattern. By changing the reference pattern parameter to match the data pattern being read, the system achieves better alignment between reference and data cells, thereby improving read voltage determination accuracy and reducing operation time.
2Reliability
If pattern cells are used to track threshold voltage distributions, then read voltage selection can be improved, but wear disparity between pattern and data cells reduces reliability
Solution Approach 1:
The patent segments the memory array into multiple regions, with different regions serving as reference pattern cells for different data patterns. By distributing reference cells across multiple regions rather than using a single dedicated reference region, the system achieves better wear distribution. Each reference region experiences wear similar to its corresponding data region, maintaining reliability while tracking threshold voltage distributions accurately.
Solution Approach 2:
The patent applies local quality by having different reference patterns in different regions of the memory array, each optimized for tracking the characteristics of local data cells. Rather than using a uniform reference scheme across the entire array, each region has reference cells with properties matched to the local data cells, ensuring both reliability and wear uniformity.
3Measurement precision
If multiple voltage steps are used for read operations to account for resistance drift, then measurement accuracy improves, but read bandwidth decreases
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple known reference patterns in the memory array before read operations. These reference patterns are prepared in advance and can be quickly selected and applied during read operations. By having the reference patterns ready beforehand, the system can rapidly compensate for resistance drift without requiring multiple sequential voltage steps, thereby maintaining measurement precision while preserving read bandwidth.
Data Source
AI summary
Systems, methods, and apparatus for a memory device. In one approach, known reference patterns are stored in a memory array. The patterns are associated with codewords stored in the memory array. A first pattern has all memory cells written to a first logic state (e.g., all logic ones), and a second pattern has all memory cells written to an opposite second logic state (e.g., all logic zeros). When a controller reads a codeword, the controller first reads memory cells of the associated reference patterns to determine data for estimating a threshold voltage distribution of memory cells in the codeword. Based on a number of memory cells of the reference patterns that snap when reading the first and second patterns, the controller selects a read voltage for reading the associated codeword.