Non-Volatile Memory Read Accuracy via Pre-Read Refresh
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Solution Overview
Problem
Non-volatile semiconductor memory devices face challenges in accurately reading data due to holes trapped at grain boundaries and charges trapped in tunnel insulating layers, which affect the reliability of read operations over time.
Innovation Solution
A refresh operation is performed before the read operation to remove trapped holes at grain boundaries and charges in the tunnel insulating layers by controlling voltage levels across various select gate lines and word lines, ensuring that memory transistors are rendered conductive to allow current flow through the memory string, thereby resetting the charge states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If stacked memory cells are used to improve bit density, then storage capacity increases, but trapped holes at grain boundaries and charges in tunnel insulating layers accumulate over time, reducing read accuracy
Solution Approach 1:
The patent applies preliminary action by performing a refresh operation before the read operation. The refresh operation pre-clears trapped holes at grain boundaries and charges in tunnel insulating layers by applying specific voltage sequences (VSGD1, VSGD2, VSGS1, VSGS2) to render memory transistors conductive, thereby removing trapped charges before they interfere with the subsequent read operation and ensuring accurate data retrieval
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting voltage levels applied to select gate lines and word lines during the refresh operation. Specific voltage parameters (VSGD1, VSGD2, VSGS1, VSGS2) are changed in sequence to control the conductive state of memory transistors, enabling the removal of trapped charges through controlled electrical parameter variation
2Measurement precision
If refresh operation is performed to remove trapped charges, then read accuracy improves, but additional time and operational steps are required
Solution Approach 1:
The patent applies periodic action by implementing a refresh operation that can be periodically executed before read operations or at scheduled intervals. The refresh operation uses periodic voltage applications (VSGD1, VSGD2, VSGS1, VSGS2) to clear trapped charges, maintaining read accuracy through regular maintenance cycles rather than continuous operation
Solution Approach 2:
The refresh operation is performed as a preliminary step before the actual read operation, clearing trapped charges in advance. This preliminary action ensures that when the read operation occurs, the memory cells are in a clean state, thereby improving read accuracy without requiring additional time during the critical read phase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of read operations by minimizing the number of trapped holes and charges, ensuring reliable data retrieval and maintaining the integrity of memory cell states.
Implementation Method 1
The control circuit performs, before the read operation, a refresh operation of rendering the selected memory cell and the non-selected memory cell conductive to conduct a current from a first end to a second end of the memory string
Implementation Method 2
The memory string includes a semiconductor layer, a charge accumulation layer, and a conductive layer. The charge accumulation layer is capable of accumulating a charge
Data Source
AI summary
A memory string includes a semiconductor layer, a charge accumulation layer, and a conductive layer. The semiconductor layer extends in a direction perpendicular to the semiconductor substrate and functions as a body of a memory cell. The charge accumulation layer may accumulate charges. The conductive layer sandwiches the charge accumulation layer with the semiconductor layer, and functions as a gate of the memory cell. The control circuit performs, before a read operation, a refresh operation of rendering the selected memory cell and a non-selected memory cell conductive to conduct a current from a first end to a second end of the memory string.


