Memory Controller Read Retry Selection for Faster Error Correction

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Solution Overview

Problem

Existing memory controllers face challenges in reducing error correction time due to unnecessary error correction decoding processes.

Innovation Solution

A memory controller is designed with a read controller and an error correction circuit that performs multiple read retry operations and first error correction decoding to identify Unsatisfied Syndrome Check (USC) values, then prioritizes second error correction decoding based on the minimum USC value to minimize unnecessary decoding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple error correction decoding operations are performed on all read retry data, then error correction reliability is improved, but error correction time increases

Engineering Contradiction:

Improveerror correction reliabilityVSAvoiderror correction time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs a first error correction decoding operation on all read retry data before performing a second error correction decoding operation. This preliminary action identifies candidate data with lower USC values, allowing the system to focus subsequent high-performance decoding only on those candidates, thus reducing overall time while maintaining reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The error correction process is divided into two distinct phases: a first error correction decoding operation that processes all read retry data to generate USC values, and a second error correction decoding operation that processes only candidate data selected based on minimum USC values. This segmentation allows the system to balance thoroughness with efficiency

Inventive Principle:

Principle #1Segmentation

2Measurement precision

If error correction decoding is performed on all read retry data, then data accuracy is improved, but processing efficiency deteriorates

Engineering Contradiction:

Improvedata accuracyVSAvoidprocessing efficiency

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

Instead of performing high-performance second error correction decoding on all read retry data (excessive action), the patent applies it only to candidate data identified by the first decoding operation (partial action). This selective approach maintains data accuracy for critical candidates while significantly improving overall processing efficiency

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The patent applies different decoding operations to different data based on their USC values. Candidate data with minimum USC values receive the high-performance second error correction decoding, while other data receive only the first error correction decoding. This local differentiation optimizes resource allocation based on actual data quality needs

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS12332741B2Memory controller performing error correction and operating method thereof

Publication Date: 2025.06.17 SK HYNIX INC

AI summary

A memory device may include a read controller and an error correction circuit. The read controller may sequentially perform a plurality of read retry operations on a memory device. The error correction circuit may perform a plurality of first error correction decodings on read data respectively acquired from the plurality of read retry operations, store a plurality of Unsatisfied Syndrome Check (USC) values respectively produced by the plurality of first error correction decodings, and perform a second error correction decoding based on read data corresponding to a minimum USC value among the plurality of USC values.