Memory Read Retry Table for Threshold Voltage Variation
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Solution Overview
Problem
Current memory systems face challenges in ensuring the reliability of read operations due to errors caused by varying threshold voltages of memory cells, which affect data retrieval and storage accuracy.
Innovation Solution
A memory system with a read retry table that adjusts sensing current based on threshold voltages, using a memory controller to manage read retry operations by selecting appropriate codes for read voltage and sensing current settings, thereby improving data retrieval reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed read voltage is used for read operations, then the operation is simple and fast, but errors occur due to varying threshold voltages of memory cells
Solution Approach 1:
The patent implements dynamic read voltage adjustment by selecting from multiple read voltage codes (RV0-RV7) based on the read retry count. The read voltage transitions from fixed to dynamically adjustable, allowing the system to adapt to varying threshold voltages of memory cells through different voltage levels, thereby improving data retrieval reliability without permanently increasing system complexity.
Solution Approach 2:
The patent changes the read voltage parameter based on the read retry operation count. When read errors occur, the system selects different read voltage codes from the read retry table, adjusting the voltage parameter to match the threshold voltage characteristics of the memory cells, thus resolving the contradiction between simple fixed-voltage operation and reliable data retrieval.
2Reliability
If read retry operations are performed multiple times with different voltage settings, then data retrieval reliability improves, but operation time increases
Solution Approach 1:
The patent pre-configures the read retry table with multiple read voltage codes (RV0-RV7) and their corresponding sensing current codes before actual read operations. This preliminary preparation allows the system to quickly switch between different voltage settings during retry operations without extensive configuration time, reducing the time penalty associated with multiple retry attempts.
Solution Approach 2:
The patent replaces iterative trial-and-error voltage adjustment with a pre-planned voltage selection strategy. Instead of randomly or sequentially testing voltage levels, the system uses the read retry table to directly select the appropriate voltage code based on the retry count, substituting a more efficient lookup-based approach that reduces operation time while maintaining reliability.
3Measurement precision
If multiple read voltage codes are stored and selected based on retry operations, then accuracy of data retrieval improves, but control complexity increases
Solution Approach 1:
The patent introduces the read retry table as an intermediary data structure that stores the mapping between read retry counts and appropriate read voltage codes. This intermediary component simplifies the control logic by providing a direct lookup mechanism, reducing the complexity of voltage selection while improving reading accuracy through precise voltage matching.
Solution Approach 2:
The patent segments the read voltage control into discrete, pre-defined levels (RV0-RV7) stored in the read retry table. Instead of requiring continuous or complex voltage adjustment mechanisms, the system divides the voltage control space into manageable segments that can be easily selected and managed, reducing control complexity while maintaining precision.
Data Source
AI summary
Provided herein is a memory system and an operation method thereof. The memory system may include a memory controller including a read retry table in which a plurality of codes are stored, and configured to output a selected code among the plurality of codes during a read retry operation. The memory system may include a memory device configured to store data, and perform the read retry operation according to the codes received from the memory controller.


