Memory System Read Retry Table Internal RAM Speed Optimization
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Solution Overview
Problem
The existing memory systems experience a decrease in speed due to frequent performance of read voltage level parameter setting commands, particularly in flash memory as the number of read levels and registers to be set increases, leading to inefficiencies in read retry operations.
Innovation Solution
A memory system and operating method that utilize a read retry table stored in internal RAM, allowing for a read retry operation with a determined read retry voltage based on the table information, and error correction to minimize the need for frequent parameter setting operations, thereby reducing operational speed degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read voltage level parameter setting commands are performed frequently to handle read failures, then read reliability is improved, but operational speed deteriorates
Solution Approach 1:
The read retry table is pre-loaded into the internal RAM of the memory device before read operations commence. This preliminary action stores offset voltage values and their corresponding set numbers in advance, eliminating the need for repeated parameter setting commands during read retry operations, thus maintaining high speed while ensuring reliability
Solution Approach 2:
The internal RAM acts as an intermediary between the external controller and the memory cells during read retry operations. By storing the read retry table locally in the internal RAM, the system avoids frequent communication with the external controller for parameter setting, thereby preventing speed degradation while maintaining read reliability
2Quantity of substance
If the number of read levels and registers to be set increases to improve storage capacity, then memory capacity is improved, but the frequency of parameter setting commands increases causing speed degradation
Solution Approach 1:
The memory device performs self-service by autonomously selecting and applying the appropriate offset voltage from the pre-loaded read retry table based on the failure mode detected during read operations. This self-service mechanism eliminates the need for the external controller to issue parameter setting commands, thereby maintaining high operational speed even as memory capacity and read levels increase
Data Source
AI summary
A memory system includes a semiconductor memory device including memory cells and an internal Random Access Memory (RAM); and a controller suitable for transmitting read retry table information to the semiconductor memory device when a read operation for the memory cells fails, wherein the internal RAM stores a read retry table during operation of the memory system, and wherein the semiconductor memory device performs a read retry operation with a read retry voltage determined based on the read retry table and the read retry table information.