Memory Controller Read Scan Selection for First Page Errors
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Solution Overview
Problem
Conventional memory sub-systems inefficiently perform first page read scans on all memory blocks regardless of storage type, leading to increased power consumption and latency due to ganged reset or dummy read operations, which are unnecessary for certain memory usages.
Innovation Solution
A memory sub-system controller selectively performs first page read scan operations based on the storage type of memory blocks, such as SLC, MLC, TLC, or QLC, avoiding unnecessary operations on SLC blocks to reduce power consumption and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If first page read scan operations are performed on all memory blocks, then first page read errors are prevented, but power consumption and latency increase
Solution Approach 1:
The patent applies different operations to different memory blocks based on their specific characteristics. SLC blocks receive no ganged reset or dummy read operations, while MLC/TLC/QLC blocks receive these operations. This local differentiation prevents first page read errors only where necessary, reducing unnecessary power consumption on SLC blocks that don't require such operations.
2Reliability
If first page read scan operations are performed on all memory blocks, then first page read errors are prevented, but system latency increases
Solution Approach 1:
The system performs ganged reset and dummy read operations only on MLC, TLC, and QLC memory blocks that are susceptible to first page read errors, while skipping SLC blocks. This selective approach reduces the total time required for first page read scan operations across the entire memory sub-system, lowering latency while maintaining reliability where needed.
3Reliability
If ganged reset or dummy read operations are performed on all memory blocks, then first page read errors are prevented, but operational efficiency decreases
Solution Approach 1:
The patent implements a selective operation strategy where SLC blocks are identified and excluded from ganged reset and dummy read operations, while MLC/TLC/QLC blocks continue to receive these operations. This improves operational efficiency by reducing the number of operations performed without compromising reliability on memory blocks that actually require error prevention.
Solution Approach 2:
The memory sub-system is segmented into different block types (SLC vs. MLC/TLC/QLC), and different operation strategies are applied to each segment. This segmentation allows the system to optimize performance for SLC blocks by skipping unnecessary operations while maintaining robust error prevention for multi-level cell blocks.
Data Source
AI summary
The present disclosure configures a memory sub-system controller to perform a first page read scan in a memory sub-system. The controller determines that a condition to prevent first page read errors has been met. The controller, in response to determining that the condition to prevent the first page read errors has been met, selects a first portion of a set of memory components. The controller determines whether the first portion corresponds to single level cell (SLC) usage and selectively performs one or more memory operations to prevent first page read errors associated with the first portion based on whether the first portion corresponds to single level cell (SLC) usage.