Memory Read Size Control for Throughput-Latency Tradeoffs

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Solution Overview

Problem

Memory systems experience increased overall latency due to longer transfer latencies on lower-speed channels caused by larger data transfers, which can be exacerbated by higher-speed channels having wait durations before data is received, leading to inefficiencies in data transmission.

Innovation Solution

A memory system controller dynamically adjusts the size of data transmitted to a host system based on monitored data requests, allowing for smaller data quantities when lower-speed channels are involved and larger quantities when higher-speed channels are available, thereby reducing wait durations and overall system latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If larger data sizes are transmitted over lower-speed channels, then more data can be transferred in parallel, but transfer latency increases significantly

Engineering Contradiction:
Improvedata transfer throughputVSAvoidtransfer latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent dynamically adjusts data read size based on channel speed characteristics. The memory system controller monitors channel performance and adapts the amount of data read from memory devices in real-time, transitioning from static to dynamic data size selection to optimize the trade-off between throughput and latency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the parameter of data read size according to channel conditions. By adjusting this critical parameter based on channel speed, the system optimizes transfer efficiency for low-speed channels while maintaining high throughput for high-speed channels, directly addressing the latency-throughput contradiction.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If larger data quantities are read from memory devices, then fewer read operations are needed, but wait durations on high-speed channels increase

Engineering Contradiction:
Improveoperational efficiencyVSAvoidwait duration
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements dynamic adjustment of data read quantities based on channel characteristics. The controller adapts the read size to match channel capabilities, ensuring that high-speed channels are not idle while low-speed channels are not overloaded, thereby reducing wait durations while maintaining operational efficiency.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system incorporates feedback mechanisms where the controller monitors channel performance and adjusts data read sizes accordingly. This closed-loop control ensures that data quantities are optimized based on actual channel conditions, reducing wait times while maintaining high operational efficiency.

Inventive Principle:
Principle #23Feedback

3Productivity

If data read size is increased to improve throughput, then more data is processed per operation, but overall system latency increases

Engineering Contradiction:
Improvedata processing throughputVSAvoidoverall system latency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies different data read sizes to different channels based on their individual characteristics. Instead of using a uniform data size for all channels, the system tailors the data quantity to each channel's speed capability, optimizing the balance between throughput and latency for each channel locally.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system dynamically selects data read sizes based on real-time channel conditions and requirements. This dynamic adaptation allows the system to maximize throughput when possible while minimizing latency when channel conditions dictate smaller transfers.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12487949B2Dynamically adjusting data read size
Publication Date: 2025.12.02 MICRON TECHNOLOGY INC
  • US12487949B2 patent drawing
  • US12487949B2 patent drawing
  • US12487949B2 patent drawing

AI summary

Methods, systems, and devices for dynamically adjusting data read size are described. A memory system controller may be configured to dynamically adjust a size of data transmitted to a host system based on determining a quantity of data requested by the host system. The memory system controller may support receiving a read command of a first data size, incrementing a counter by the first data size, requesting the data from a memory device according to a second data size, and transmitting the data from the memory device according to a third data size based on the counter. The memory system controller may determine the counter does not satisfy a threshold and configure the third data size as a relatively small quantity of data. However, the memory system controller may determine the counter satisfies the threshold and configure the third data size as a relatively large quantity of data.