Semiconductor Memory Read Operation Stabilizing Threshold Voltage
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently performing read operations due to variations in threshold voltages caused by electric field interactions between charge storage layers, leading to issues with data retention and erroneous readings.
Innovation Solution
The semiconductor memory device incorporates a hole charge operation before data read, where specific voltages are applied to generate holes in the channel regions of select transistors, reducing threshold voltage variations and improving data read accuracy by maintaining holes in these regions during the read process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If read voltage is supplied to conductive layers for data reading, then data can be read from memory cells, but threshold voltage variations occur due to electric field interactions between charge storage layers
Solution Approach 1:
The patent applies preliminary anti-action by performing a hole charge operation before the read operation. This pre-charges the channel regions of select transistors with holes, creating a counter-effect that compensates for the threshold voltage variations that will occur during the subsequent read operation. By establishing this opposing charge state in advance, the patent prevents the harmful electric field interactions from causing erroneous readings.
Solution Approach 2:
The patent implements preliminary action by executing the hole charge operation as a preparatory step before data reading. This preliminary charging of channel regions with holes ensures that when the read operation subsequently occurs, the threshold voltages are already stabilized and less susceptible to variations caused by electric field interactions between charge storage layers.
2Reliability
If charge storage layers are used to store data, then data retention is achieved, but electric field interactions cause threshold voltage variations leading to erroneous readings
Solution Approach 1:
The patent introduces an intermediary mechanism by utilizing the channel regions of select transistors as a mediator between the charge storage layers and the read operation. By charging these channel regions with holes, the patent creates an intermediate charge state that buffers and mediates the electric field interactions between charge storage layers, preventing direct harmful effects on read accuracy while preserving data retention capabilities.
3Quantity of substance
If multiple conductive layers are arranged closely for high density, then storage capacity increases, but electric field interactions between layers increase threshold voltage variations
Solution Approach 1:
The patent applies self-service by enabling the select transistors to serve their dual function: selecting memory cells during read operations and simultaneously stabilizing threshold voltages through self-charging with holes. This self-service mechanism allows the device to compensate for its own threshold voltage variations caused by close proximity of conductive layers, without requiring additional external intervention or complex control circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data read accuracy by stabilizing threshold voltages and reducing hot electron generation, thereby improving data retention and minimizing erroneous readings.
Implementation Method 1
variations in threshold voltages caused by electric field interactions between charge storage layers
Implementation Method 2
a read voltage is supplied to an n-th first conductive layer... a read pass voltage larger than the read voltage is supplied to at least apart of the plurality of first conductive layers
Data Source
AI summary
A semiconductor memory device includes: first conductive layers; second conductive layers; a first semiconductor layer disposed between the first conductive layers and the second conductive layers; a charge storage layer that includes a first part disposed between the plurality of first conductive layers and the first semiconductor layer and a second part disposed between the plurality of second conductive layers and the first semiconductor layer; and a first wiring electrically connected to the first semiconductor layer. The semiconductor memory device is configured such that a read operation and a first operation performed before the read operation are performable. In the first operation: a first voltage is supplied to the first wiring; and a second voltage smaller than the first voltage is supplied to an n-th second conductive layer counted from the one side in the first direction.