Memory Read Status Signaling With Concurrent Command Input
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face challenges in efficiently managing the status of read operations across multiple semiconductor storage devices, particularly in determining the ready/busy state of individual devices within a memory system.
Innovation Solution
A memory system design that includes a controller device to instruct semiconductor storage devices to output a ready/busy state through a status register, allowing for simultaneous command and address data input while managing the status of read operations across multiple devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single signal pad is used for both outputting ready/busy state and inputting commands, then the number of signal pads is reduced, but the ability to simultaneously manage multiple devices and operations is deteriorated
Solution Approach 1:
The patent implements time-division multiplexing where the second signal pad alternates between inputting command data and address data in different time periods. During the first time period, the pad receives command data; during the second time period, it receives address data. This periodic switching allows efficient use of a single signal pad while maintaining the ability to manage multiple devices through the status register mechanism.
2Device complexity
If the memory system waits for read operation completion before accepting next command, then operation sequencing is simplified, but time utilization is reduced
Solution Approach 1:
The patent enables preliminary action by allowing the controller to input the next command data or address data through the second signal pad during the time period when the current read operation is being executed. The status register continuously updates and outputs the ready/busy state, allowing the controller to prepare subsequent operations in advance without waiting for current operations to complete, thus improving time utilization while maintaining operational integrity.
3Measurement precision
If status register is implemented to output ready/busy state, then operation status monitoring is improved, but device complexity increases
Solution Approach 1:
The status register is designed with multi-functionality, serving both as a storage element for operation status information and as an output buffer that continuously provides ready/busy state signals. This single component performs multiple functions: tracking read operation completion, interfacing with the controller through the first signal pad, and enabling the controller to make informed decisions about subsequent operations, thereby improving status monitoring without proportionally increasing overall device complexity.
Data Source
AI summary
According to one embodiment, a memory system includes semiconductor storage devices and a controller device. Each semiconductor storage device includes: first and second signal pads through which command data and address data for instructing one of the semiconductor storage devices to perform a read operation are transmitted; and a status register. A controller device is configured to instruct the one of the semiconductor storage devices to provide a status of the read operation. The one of the semiconductor storage devices is configured to, upon receiving the instruction to provide the status of the read operation, output a ready/busy state stored in the status register through the first signal pad while allowing an input of another command data and another address data through the second signal pad.