Semiconductor Memory Read Level Correction via Adjacent Cell Threshold Detection
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Solution Overview
Problem
The challenge in semiconductor memory devices is accurately reading data from memory cells due to capacitance variations between adjacent floating gates, which affects the threshold voltage and requires a method to determine appropriate correction values for reliable data retrieval.
Innovation Solution
A semiconductor memory device with a memory cell array that includes a control portion to read the threshold level of adjacent memory cells, apply correction levels to the read-out data, and use error correction mechanisms to ensure accurate data retrieval by accounting for capacitance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is written into memory cells with miniaturization, then storage capacity is improved, but capacitance coupling between adjacent floating gates causes threshold voltage rise in adjacent cells
Solution Approach 1:
The patent applies preliminary action by detecting the threshold voltage of adjacent memory cells before reading the target cell, and pre-calculating the correction value. This allows the capacitance coupling effect to be compensated in advance, enabling accurate data reading even as miniaturization increases coupling strength between adjacent floating gates.
Solution Approach 2:
The patent implements feedback by measuring the actual threshold voltage of adjacent cells and using this information to adjust the read level of the target cell. The correction value derived from adjacent cell measurements is fed back to modify the reading process, compensating for the capacitance coupling effect that arises with higher storage capacity.
2Measurement precision
If correction value is applied to compensate for adjacent cell threshold voltage rise, then data reading accuracy is improved, but device complexity increases due to additional detection and correction mechanisms
Solution Approach 1:
The patent uses copying by creating a dummy memory cell that replicates the structure and characteristics of actual memory cells. This dummy cell serves as a reference for measuring capacitance coupling effects, allowing the system to determine correction values without adding complex detection circuits to every memory cell, thus improving reading accuracy while limiting the increase in device complexity.
Solution Approach 2:
The patent applies parameter changes by adjusting the read level of memory cells based on detected threshold voltage variations. Instead of changing the physical structure or adding complex hardware, the system modifies the electrical parameters (read levels) dynamically based on measured conditions, achieving improved accuracy with minimal complexity increase.
3Measurement precision
If threshold voltage of adjacent cells is detected for correction, then read level accuracy is improved, but measurement time and processing steps increase
Solution Approach 1:
The patent applies preliminary action by measuring the threshold voltage of adjacent cells and calculating correction values during the write process or before the read operation. This advance preparation allows the correction to be applied instantly during reading without adding significant time delay, as the measurement and calculation are completed in advance.
Solution Approach 2:
The patent merges the correction measurement process with the normal read/write operations by integrating the dummy cell measurements into the existing memory array operations. This combining of functions allows threshold voltage detection and correction value determination to occur as part of the standard operational sequence, reducing additional time requirements while maintaining read level accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate data reading and correction, even with varying capacitance between adjacent cells, enhancing the reliability and precision of data storage and retrieval in semiconductor memory devices.
Implementation Method 1
a control portion which is formed so as to read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array
Implementation Method 2
a storage portion which is formed so as to store a correction level
Data Source
AI summary
In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.