Non-Volatile Memory Read Timing for Bit Line Voltage Control
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Solution Overview
Problem
Non-volatile memory operations fail due to erroneous timing sequences of signals, particularly when process variations in semiconductor manufacturing result in inconsistent operation speeds of semiconductor devices, leading to failed read results.
Innovation Solution
A non-volatile memory system with a controlling circuit that includes a processing circuit, decoder, driver, timing controller, and sense amplifier, where the timing controller generates precharge and reset signals to accurately manage bit line voltages, and the use of core and I/O devices with different voltage stress capabilities helps mitigate process variation effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If process variations in semiconductor manufacturing are present, then device operation speeds become inconsistent, but manufacturing precision remains constrained by process variability
Solution Approach 1:
The patent changes the timing parameters of control signals dynamically. The timing controller adjusts the timing sequences of precharge signals and reset signals based on detected operation speeds, compensating for process variations without requiring tighter manufacturing control
Solution Approach 2:
The patent implements a feedback mechanism where the timing controller detects the actual operation speed of semiconductor devices and uses this information to adjust subsequent timing sequences, ensuring reliable operation despite manufacturing variations
2Reliability
If timing sequences of control signals are not precisely controlled, then memory operations may fail, but adding complex timing control mechanisms increases device complexity
Solution Approach 1:
The timing controller generates precharge signals and reset signals in advance with predetermined timing sequences. This preliminary timing control ensures that bit lines are properly prepared before read operations, preventing operation failures without requiring complex real-time adjustments
Solution Approach 2:
The timing controller acts as an intermediary between the processing circuit and the memory array, mediating timing sequences of control signals. It translates processing circuit commands into precisely timed control signals for the memory array, simplifying the overall system architecture while ensuring reliable operation
3Measurement precision
If bit line voltages are not accurately controlled during read operations, then read data accuracy decreases, but improving voltage control precision increases circuit complexity
Solution Approach 1:
The timing controller generates precharge signals that activate sense amplifiers to pre-charge bit lines to a first predetermined voltage before read operations. This preliminary voltage setup ensures accurate read data by establishing proper initial conditions without requiring complex real-time voltage adjustment circuits
Solution Approach 2:
The timing controller periodically generates reset signals to adjust selected bit lines to a second predetermined voltage. This periodic voltage resetting ensures that bit lines maintain accurate voltage levels throughout operation, improving read data accuracy through rhythmic control rather than continuous complex adjustment
Data Source
AI summary
A non-volatile memory includes a memory array and a controlling circuit. The memory array includes plural word lines and plural bit lines. The controlling circuit includes a processing circuit, a decoder, a driver, a timing controller and a sense amplifier. The decoder is connected with the processing circuit. The driver is connected with the decoder and the plural word lines. The timing controller is connected with the processing circuit. The sense amplifier is connected with the decoder, the timing controller and the plural word lines.