Memory Read Timing Control via Data Pattern Effect
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Solution Overview
Problem
Non-volatile memory devices face variability in read and program operation times due to process and data pattern variations, leading to inconsistent performance across memory cells.
Innovation Solution
A memory apparatus and method that adjust bit line settling time and kick voltage based on the probability of neighboring memory cells having different data states, optimizing read operations by offsetting these parameters to improve timing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fixed read timing is used for all memory cells, then circuit complexity is reduced, but read operation time varies greatly due to process and data pattern variations
Solution Approach 1:
The patent implements dynamic read timing adjustment by modifying the read clock timing based on detected data patterns in neighboring memory cells. The system transitions from fixed timing to adaptive timing that responds to capacitive coupling conditions, allowing the read operation to accommodate variations in capacitive effects without increasing overall system complexity.
Solution Approach 2:
The system changes the timing parameter of the read clock dynamically based on the detected data pattern. By adjusting the read clock timing offset according to the capacitive coupling conditions indicated by neighboring cell states, the system optimizes read operation reliability without requiring completely new circuit architecture.
2Manufacturing precision
If standard read clock timing is used without adjustment, then manufacturing precision requirements are reduced, but read operation time varies due to capacitive coupling effects
Solution Approach 1:
The patent employs feedback by detecting the data pattern in neighboring memory cells and using this information to adjust the read clock timing. This feedback mechanism allows the system to compensate for capacitive coupling effects that arise from process variations, maintaining consistent read operation times without requiring tighter manufacturing tolerances.
3Reliability
If read clock timing is adjusted based on neighboring cell states, then read operation consistency is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by adjusting the read clock timing specifically for regions affected by capacitive coupling, rather than uniformly across all memory cells. The timing adjustment is localized based on the detected data pattern in neighboring cells, providing targeted compensation without unnecessarily complicating the control of unrelated memory regions.
4Device complexity
If uniform settling time is used for all bit lines, then control circuit complexity is reduced, but read accuracy deteriorates due to data pattern variations
Solution Approach 1:
The system dynamically adjusts the bit line settling time based on the detected data pattern in neighboring memory cells. This dynamic adjustment ensures that bit lines experiencing capacitive coupling effects are given sufficient settling time, while bit lines not affected by such effects maintain faster operation, thereby preserving read accuracy without uniformly increasing settling time for all lines.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the consistency and efficiency of read operations by accounting for neighboring cell states, thereby reducing variability and improving overall memory performance.
Implementation Method 1
the differing combinations of high or low voltages applied to a particular block of non-volatile memory and timing of transitions between the various voltages can influence programming and read operation times due to capacitive coupling between adjacent bit lines or word lines
Data Source
AI summary
A memory apparatus and method of operation is provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings coupled to one of a plurality of bit lines and are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to read each of the memory cells in a read operation. For each one of the memory cells, the control means is also configured to offset at least one of a bit line settling time and a kick voltage during the read operation based on a probability of at least one neighboring one of the plurality of bit lines being coupled to the memory cells retaining the threshold voltage corresponding to a different one of the plurality of data states than the one of the memory cells.