Memory Multiple-Read Timing to Reduce Read Disturb

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Multiple-read operations in memory sub-systems lead to read disturb and increased error rates due to continuous reading without intervening erase operations, causing adjacent memory cells to become corrupted, and result in communication interface bottlenecks that increase wait times and read stress.

Innovation Solution

Implementing a multiple-read delay before the initial sense sequence of a multiple-read operation to realign the completion of the first read with the completion of the previous page data transfer, reducing wait times and eliminating or minimizing read disturb and stress.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple-read operations are executed continuously without delay, then data retrieval speed is improved, but read disturb increases and error rates increase

Engineering Contradiction:
Improvedata retrieval speedVSAvoiddata integrity
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements periodic delay intervals between multiple-read operations on the same memory page. Instead of continuous reading, the system introduces scheduled pauses that allow the memory cells to recover, reducing read disturb effects while maintaining efficient data retrieval through batched read operations.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent performs preliminary checks and prepares subsequent read operations in advance. By anticipating future read requests and preparing the memory system accordingly, the system can execute reads more efficiently while ensuring that necessary recovery actions are taken beforehand to prevent read disturb.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If multiple-read operations are executed continuously without delay, then throughput is improved, but wait times increase due to communication interface bottlenecks

Engineering Contradiction:
Improveread throughputVSAvoidwait time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent introduces periodic delays in the read operation schedule that align with the communication interface's data transfer capacity. This synchronization ensures that read operations complete just as data transfer becomes available, eliminating idle wait times while maintaining high throughput through optimized batching.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent implements feedback mechanisms that monitor the completion status of data transfers and adjust subsequent read operation timing accordingly. By using this feedback information, the system dynamically optimizes read schedules to match actual interface availability, reducing wait times while maintaining high productivity.

Inventive Principle:
Principle #23Feedback

3Productivity

If multiple-read operations are executed continuously without delay, then operational efficiency is improved, but read stress on memory cells increases

Engineering Contradiction:
Improveoperational efficiencyVSAvoidread stress
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent implements periodic read operations with scheduled intervals that allow memory cells to recover from stress. This rhythmic reading pattern maintains operational efficiency by keeping the memory system active and productive while preventing excessive read stress through mandatory recovery periods.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent takes preliminary anti-actions by introducing delays and recovery periods before read stress becomes problematic. By anticipating potential stress accumulation and counteracting it with scheduled pauses, the system maintains high operational efficiency while preventing harmful stress effects on memory cells.

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS20260023500A1Delayed execution of a multiple-read operation
Publication Date: 2026.01.22 MICRON TECHNOLOGY INC
  • US20260023500A1 patent drawing
  • US20260023500A1 patent drawing
  • US20260023500A1 patent drawing

AI summary

A memory device including a memory array and control logic, operatively coupled with the memory array, to perform operations including identifying, at a first time, a request to execute a multiple-read operation including a first sense sequence to read first data associated with a first page of multiple pages of a memory device and a second sense sequence to read second data associated with a second page of the multiple pages of the memory device. Execution of the multiple-read operation is caused to be delayed to a second time. At the second time, the execution of the multiple-read operation is caused, where the first sense sequence and a transfer of data associated with a prior operation via a communication interface associated with the memory device complete at substantially a same time.