Memory Read Timing Margin Adjustment via Delay Tables
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Solution Overview
Problem
Integrated circuits with on-chip memory face challenges in adjusting delay times for read and write operations due to changes in supply voltage and clock frequency, affecting performance and power consumption.
Innovation Solution
A control unit accesses tables to select and set appropriate delay times for memory operations based on changes in operating points, such as supply voltage and clock frequency, to ensure valid data output and optimize performance and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the supply voltage is increased to support higher performance, then the read operation speed is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic adjustment of delay times based on changing operating conditions. The system monitors supply voltage and clock frequency changes, and dynamically selects appropriate delay values from predefined tables to optimize memory operation timing at each operating point, enabling the system to adapt to varying performance and power requirements
Solution Approach 2:
The patent changes the delay time parameter in response to supply voltage and clock frequency changes. By storing multiple delay values corresponding to different operating points and selecting the appropriate delay based on current operating conditions, the system optimizes the balance between speed and power consumption
2Use of energy by moving object
If the supply voltage is reduced to save power, then the power consumption is reduced, but the read operation time increases
Solution Approach 1:
The system dynamically adjusts delay times based on reduced supply voltage conditions. When voltage reduction is detected, the system selects longer delay values from predefined tables that account for the slower operation at lower voltages, ensuring reliable memory operations while maintaining power savings
Solution Approach 2:
The patent adjusts the delay time parameter in response to supply voltage reductions. By selecting appropriate delay values from tables that correspond to lower operating points, the system ensures sufficient time for sense amplifiers to accurately reflect stored data values even at reduced power consumption levels
3Speed
If the clock frequency is increased to support higher performance, then the processing speed is improved, but the delay time for valid data output must be reduced
Solution Approach 1:
The system dynamically adjusts the delay time based on clock frequency changes. When higher clock frequencies are detected, the system selects shorter delay values from predefined tables, allowing the memory operation to complete within the reduced time window provided by faster clock cycles
Solution Approach 2:
The patent changes the delay time parameter in response to clock frequency increases. By selecting appropriate delay values from tables corresponding to different frequency operating points, the system optimizes the balance between processing speed and the time required for valid data output
4Adaptability or versatility
If multiple delay tables are used for different memory arrays, then the adaptability to different operating points is improved, but the device complexity increases
Solution Approach 1:
The patent divides the delay time storage into multiple separate tables, with each table dedicated to a specific memory array. This segmentation allows each table to be optimized for its corresponding memory array's characteristics while maintaining a systematic approach to managing delay times across the entire system
Solution Approach 2:
The control unit is designed to universally handle multiple delay tables and select from them based on the active memory array and operating point. This universal control mechanism manages the complexity of multiple tables while providing adaptability to different memory arrays and operating conditions
Data Source
AI summary
An apparatus and method for changing the extra margin adjustment (EMA) for a memory is disclosed. A control unit may access a table responsive to an indication of a change of operating point. The table includes a number of different delay times, each of which corresponds to a particular operating point. The control unit may select the delay time that corresponds to the new operating point to which the memory operation is being changed. The control unit may further convey an indication of the selected delay time to the memory, thereby causing the memory to operate according thereto.