Semiconductor Memory Read Timing for Layer Resistance Variation
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently managing the application of voltages to different conductive layers during operations, leading to potential misinterpretation of memory cell states due to varying wiring resistances, which affects the reliability of read operations.
Innovation Solution
The semiconductor memory device employs distinct operation parameters for different conductive layers, including adjusted voltage magnitudes and supply times, to ensure appropriate charging based on the specific wiring resistance of each layer, thereby improving the reliability of read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the same voltage parameters are applied to all conductive layers, then the device structure and operation are simple, but read operation reliability deteriorates due to varying wiring resistances
Solution Approach 1:
The patent applies different voltage parameters (magnitude and supply time) to different conductive layers based on their specific wiring resistance characteristics. Each conductive layer is configured with optimized parameters tailored to its local electrical properties, ensuring reliable read operations while accounting for variations in wiring resistance across the device structure.
Solution Approach 2:
The patent changes the operational parameters (voltage magnitude and supply time) for different conductive layers to compensate for wiring resistance variations. By adjusting these parameters locally for each layer, the system achieves consistent read operation reliability despite differences in electrical characteristics across the stacked memory structure.
2Reliability
If voltage magnitude and supply time are increased for all layers, then charging reliability improves, but energy consumption increases
Solution Approach 1:
Instead of uniformly increasing voltage parameters across all layers, the patent applies locally optimized voltage magnitudes and supply times to each conductive layer based on its specific wiring resistance. This ensures each layer receives just enough energy for reliable charging without excessive energy consumption, achieving energy efficiency while maintaining charging reliability.
3Quantity of substance
If the number of conductive layers is increased to enhance memory capacity, then storage density improves, but wiring resistance variations increase affecting read accuracy
Solution Approach 1:
The patent addresses wiring resistance variations in high-capacity stacked memory by applying different voltage parameters to each conductive layer. This local optimization ensures that even as the number of layers increases, each layer's memory cell state can be accurately determined by compensating for its specific wiring resistance characteristics, maintaining read accuracy despite increased storage density.
Data Source
AI summary
A semiconductor memory device includes: conductive layers including a first range and a second range; a first semiconductor layer opposed to the conductive layers in the first range; a second semiconductor layer opposed to the conductive layers in the second range; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. When a sense time of the first bit line when a predetermined operation is performed on a first memory cell including a first electric charge accumulating portion is assumed to be a first operation parameter and a sense time of the second bit line when the predetermined operation is performed on a second memory cell including a second electric charge accumulating portion is assumed to be a second operation parameter, the second operation parameter differs from the first operation parameter.