Memory Read Error Handling with TVS Voltage Offset Bins
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Solution Overview
Problem
Existing memory sub-systems face high bit error rates due to temporal voltage shift (TVS) in non-volatile memory devices, which is exacerbated by Program Erase Cycles, higher temperatures, and higher program voltages, leading to inefficient error handling strategies.
Innovation Solution
Implementing block family-based error avoidance strategies, where memory cells are grouped into block families with similar voltage distributions, and dynamic tracking of temporal voltage shift to apply appropriate voltage offsets for read operations, with periodic calibration and re-synchronization upon power-up to minimize bit errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error handling strategies are used in memory sub-systems, then device complexity is reduced, but bit error rates increase due to temporal voltage shift
Solution Approach 1:
The patent segments memory blocks into different voltage offset bins based on their temporal voltage shift characteristics. By dividing the memory space into multiple bins with distinct voltage offset profiles, the system can apply targeted error handling strategies to each segment, improving overall reliability without uniformly increasing complexity across the entire memory sub-system.
Solution Approach 2:
The patent dynamically changes voltage offset parameters based on observed temporal voltage shift patterns. By monitoring and adjusting voltage offset values for different block bins, the system adapts to changing memory characteristics over time, thereby reducing bit error rates while maintaining manageable error handling complexity through parameter-based differentiation.
2Reliability
If calibration operations are performed frequently to minimize bit errors, then bit error rates decrease, but productivity decreases due to increased calibration overhead
Solution Approach 1:
The patent implements periodic calibration operations scheduled at specific intervals or triggers rather than continuous calibration. By performing calibration only when necessary (e.g., after power cycles or at predetermined time intervals), the system maintains low bit error rates while minimizing the productivity impact of calibration overhead.
Solution Approach 2:
The patent performs calibration selectively on only those memory blocks that require it, based on their voltage offset bin classification. Rather than calibrating the entire memory sub-system uniformly, the system applies calibration partially to specific blocks, reducing overall calibration overhead while maintaining reliability where needed.
3Reliability
If voltage offsets are applied to compensate for temporal voltage shift, then bit error rates improve, but manufacturing precision requirements increase
Solution Approach 1:
The patent pre-characterizes memory blocks and assigns them to voltage offset bins during manufacturing or initial operation, before actual data storage begins. By determining and storing the appropriate voltage offset for each block in advance, the system reduces the precision requirements during normal operation, as the voltage offset parameters are predetermined rather than requiring high-precision real-time adjustment.
Data Source
AI summary
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to detect a power-up state of the memory device following a power loss event; detect a read error with respect to data residing in a block of the memory device, wherein the block is associated with a current voltage offset bin; and perform temporal voltage shift (TVS)-oriented calibration for associating the block with a new voltage offset bin.