Multi-level Memory Read Voltage Selection via Address Encoding
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Solution Overview
Problem
Multi-level cell memory devices require significant time for read operations due to the need for multiple sequential data read voltage applications across various threshold voltage states, which slows down data reading processes.
Innovation Solution
A method for selecting a reduced number of read voltages based on information set at the address of the multi-level cell, allowing for the determination of multi-level data using fewer voltage applications, thereby reducing read operation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple sequential data read voltages are applied to determine multi-level cell states, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent applies preliminary action by setting a portion of the cell address in advance to indicate the threshold voltage state range before the read operation begins. This pre-set address information allows the read circuit to directly select and apply the appropriate read voltage without sequentially testing multiple voltages, thereby reducing read operation time while maintaining accurate threshold voltage state determination.
2Reliability
If multiple sequential read voltages are applied during data read operation, then reliability is improved, but productivity decreases
Solution Approach 1:
The method performs preliminary action by pre-configuring the address portion to encode information about the threshold voltage state range before the read operation. This allows the system to directly apply the correct read voltage based on the pre-set address, ensuring reliable data reading while significantly improving productivity by eliminating sequential voltage application delays.
3Measurement precision
If multiple read voltages are sequentially applied to read multi-level cell data, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by using preliminary action - the address portion is pre-set to indicate the threshold voltage state range, which directly controls the read voltage selection. This eliminates the need for complex sequential voltage control circuits and timing mechanisms, while maintaining accurate multi-level data determination through direct voltage application based on the pre-configured address.
Data Source
AI summary
Methods for operating a nonvolatile memory device including multi-level cells configured to store at least n logic states, where n is equal to or greater than four are provided. The methods may include selecting at least one read voltage for a read operation based on information set at a portion of an address of the respective one of the multi-level cells, and determining multi-level data stored in the respective multi-level cell using the at least one selected read voltage.