Memory Read Voltage Allocation for Threshold Shift Accuracy
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Solution Overview
Problem
Existing memory systems face challenges in accurately reading data due to variations in threshold voltages of memory cell transistors over time, which can lead to incorrect data retrieval, especially in non-volatile memory systems.
Innovation Solution
The memory system employs a controller that calculates and updates both common and individual read voltages based on the threshold voltage distribution of memory cell transistors, using a read voltage selection unit to apply the appropriate voltage for each block, ensuring accurate data reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a fixed common read voltage is used for all blocks, then the device complexity is reduced, but the data reading accuracy deteriorates due to threshold voltage variations
Solution Approach 1:
The patent segments the read voltage management by dividing blocks into two categories: those that use the common read voltage and those that use individually calculated read voltages. This segmentation allows the system to apply complex individualized voltage adjustment only where necessary while maintaining simplicity for the majority of blocks, thus resolving the contradiction between device complexity and reading accuracy.
Solution Approach 2:
The patent implements local quality by allowing different read voltage strategies for different blocks based on their specific characteristics. Blocks with significant threshold voltage variations receive individually calculated read voltages, while blocks with stable characteristics use the common read voltage. This localized approach optimizes reading accuracy for each block without unnecessarily increasing overall system complexity.
2Measurement precision
If individually calculated read voltages are used for all blocks, then the data reading accuracy is improved, but the device complexity and processing time increase
Solution Approach 1:
The patent applies partial action by calculating individual read voltages for only those blocks that require it, rather than for all blocks. The controller determines which blocks need individualized voltage adjustment based on threshold voltage distribution analysis, and applies the more complex voltage management strategy only to those specific blocks, thereby improving accuracy without proportionally increasing overall system complexity.
Solution Approach 2:
The patent changes the read voltage parameter dynamically based on block-specific characteristics. For blocks where threshold voltage variations affect reading accuracy, the system adjusts the read voltage parameter individually. For other blocks, the system maintains the common read voltage parameter, thus optimizing accuracy while minimizing the impact on device complexity.
3Productivity
If read voltage is not updated after write processing, then the processing speed is maintained, but the data reading accuracy deteriorates due to threshold voltage shifts
Solution Approach 1:
The patent implements preliminary action by calculating and storing individual read voltages for blocks that are likely to require adjustment after write processing. By preparing these voltage values in advance and having them ready when needed, the system can update read voltages without significant processing delays, thus maintaining productivity while improving reading accuracy.
Solution Approach 2:
The patent employs feedback mechanisms where the controller monitors threshold voltage distributions and determines when read voltage updates are necessary. This feedback-driven approach ensures that voltage updates occur only when needed, avoiding unnecessary processing delays while maintaining reading accuracy. The system continuously adapts to voltage shifts based on actual performance data.
Data Source
AI summary
According to one embodiment, a memory system includes 1st-5th sub-memory regions and a controller, the controller being configured to: calculate a 1st voltage of the 1st sub-memory region in 1st processing; calculate a 2nd voltage of the 4th sub-memory region in 2nd processing; before the 1st processing, use a 3rd voltage when reading the 1st and 2nd sub-memory regions, and the 4th and the 5th sub-memory regions, and use a 4th voltage of the 3rd sub-memory region when reading the 3rd sub-memory region; use the 1st voltage when reading the 1st sub-memory region, use a 5th voltage calculated by using the 1st voltage when reading the 2nd, the 4th, and the 5th sub-memory regions, use a 6th voltage calculated by using the 2nd voltage when reading the 2nd and the 5th sub-memory regions.