Memory Subsystem Read Voltage Adjustment via Programmed Bit Count Feedback
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Solution Overview
Problem
Memory cells in memory sub-systems experience changes in threshold voltage over time due to programming, sensing, and erase cycles, leading to erroneous read operations, which existing technologies fail to accurately correct without costly calibration algorithms.
Innovation Solution
A feedback system dynamically adjusts read voltage levels by establishing a target ratio of programmed bits to erased bits during programming, measuring the cumulative number of programmed bits during read operations, and comparing it to the target ratio to adjust the read voltage level, eliminating the need for continuous calibration and tracking changes in threshold voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If costly calibration algorithms are used to correct threshold voltage changes, then read accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements a feedback mechanism where the system performs read operations at multiple voltage levels, counts the number of programmed bits detected, and uses this count to dynamically adjust the read voltage level. This closed-loop feedback approach maintains read accuracy by automatically compensating for threshold voltage drift without requiring complex external calibration algorithms, thus resolving the contradiction between reliability and device complexity
Solution Approach 2:
The memory sub-system performs self-calibration by using its own read operations to detect threshold voltage changes and automatically adjust its read voltage levels. The system serves its own calibration needs by monitoring programmed bit counts and adapting its operation accordingly, eliminating the need for costly external calibration algorithms and reducing device complexity while maintaining read accuracy
2Reliability
If continuous calibration is performed to track threshold voltage changes, then read accuracy is maintained, but time efficiency decreases due to additional calibration overhead
Solution Approach 1:
Instead of continuous calibration, the patent implements periodic calibration through read operations that occur at defined intervals during normal memory operation. The system performs read operations to detect programmed bit counts at specific time points, adjusts voltage levels based on these periodic measurements, and maintains accuracy without constant calibration overhead, thus resolving the contradiction between reliability and time efficiency
Solution Approach 2:
The patent integrates calibration functionality into regular read operations, allowing the system to perform both data retrieval and threshold voltage monitoring simultaneously. By making the calibration process continuous with useful read actions rather than separate overhead operations, the system maintains read accuracy while minimizing time loss, as the same read operations serve dual purposes of data access and calibration
3Reliability
If read voltage levels are adjusted dynamically, then read accuracy improves, but operation latency increases
Solution Approach 1:
The patent performs voltage level adjustments based on programmed bit count detection during idle periods or between read operations. By preparing and adjusting voltage levels in advance during non-critical time windows, the system ensures accurate read operations are ready when needed without adding latency to actual data retrieval, thus resolving the contradiction between reliability and operation latency
Solution Approach 2:
The system implements dynamic voltage adjustment where read voltage levels are adaptively changed based on real-time detection of programmed bit counts. This dynamic approach allows the system to optimize voltage levels on-the-fly during operation, improving read accuracy while minimizing latency by making adjustments only when necessary based on actual operating conditions rather than using fixed static voltage levels
Data Source
AI summary
A target value of programmed bits of a first programming distribution of a set of programming distributions associated with a memory device is established. A first read voltage level is applied to a wordline portion of the memory device. A count of programmed bits in the set of programming distributions corresponding to the first read voltage level is determined. A measured ratio of the programmed bits of the first programming distribution to the count of programmed bits in the set of programming distributions is determined. The target value is compared to the measured ratio to determine a comparison result. An action is executed in view of the comparison result.