Memory Read Voltage Calibration Using Error-Bit Feedback

The patent performs preliminary calibration of the read voltage level during manufacturing or initial setup to establish an accurate baseline voltage position. This preliminary action ensures that the default read voltage level is already optimized, reducing or eliminating the need for subsequent optimal read level search operations during normal operation, thereby improving reading accuracy without increasing energy consumption.

The patent implements a self-calibration mechanism where the memory device automatically monitors and adjusts its own read voltage level based on detected threshold voltage shifts in memory cells. This self-service approach maintains optimal reading accuracy dynamically without requiring external intervention or energy-intensive search operations, as the system uses its own operational data to make real-time voltage adjustments.

The patent establishes the optimal read voltage level as a default value during manufacturing or initial calibration, so that normal read operations can proceed using this pre-optimized voltage without requiring repeated search operations. This preliminary setup ensures high reading accuracy while maintaining fast data read performance, as the system only performs voltage adjustments when necessary rather than during every read operation.

The patent implements a feedback mechanism where the system monitors reading accuracy and threshold voltage shifts, and only triggers read level adjustments when actual deviations are detected. This feedback-based approach maintains high data read performance by avoiding unnecessary adjustments, while still ensuring reading accuracy by performing corrections only when the monitored parameters indicate a need for calibration.

The patent implements a self-calibration mechanism where the memory device automatically detects threshold voltage shifts in its own memory cells and adjusts the read voltage level accordingly. This self-service approach maintains high data reading speed by using the default voltage level for normal operations, while simultaneously improving reliability by automatically correcting voltage offsets when detected, thus reducing error bit rates without sacrificing performance.

The patent uses feedback from error detection mechanisms to trigger selective calibration of the read voltage level. During normal high-speed read operations, the system monitors for errors caused by threshold voltage offset, and only performs voltage adjustments when error rates exceed thresholds. This feedback-based strategy maintains high data reading speed while improving reliability by calibrating only when necessary.