Memory Read Voltage Correction for Threshold Drift Reliability
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Solution Overview
Problem
Current memory systems face challenges in maintaining data read reliability due to changes in threshold voltage distributions of memory cell transistors caused by stress and wear, leading to increased fail bit counts and error corrections failures.
Innovation Solution
A memory system that includes a semiconductor storage device and a memory controller, which performs a patrol operation to correct read voltages based on fail bit counts and fail ratios, updating correction values to optimize read voltages and reduce errors, and utilizes a soft determination decoding process with LLR tables to improve error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read voltage is used to read data from memory cells, then data can be retrieved, but threshold voltage changes due to stress and wear cause fail bits and read errors
Solution Approach 1:
The system performs patrol operations before normal read operations to detect threshold voltage distribution changes and calculate correction values in advance. By proactively identifying and correcting threshold voltage shifts due to stress and wear, the system prepares the read voltage parameters beforehand, preventing read errors before they occur during normal operation.
Solution Approach 2:
The system continuously monitors fail bit counts during patrol operations and uses this feedback to dynamically adjust correction values for read voltages. The correction value calculation based on fail bit counts creates a closed-loop feedback mechanism that adapts to threshold voltage changes, maintaining data read reliability despite ongoing stress and wear effects.
2Measurement precision
If correction values are adjusted based on fail bit counts, then read voltage accuracy improves, but system complexity increases due to patrol operations and correction calculations
Solution Approach 1:
The memory system performs self-diagnosis and self-correction through automated patrol operations. The control circuit automatically detects threshold voltage shifts, calculates appropriate correction values based on fail bit counts, and adjusts read voltages without external intervention. This self-service approach simplifies the overall system architecture by integrating correction functionality directly into the memory controller rather than requiring separate complex correction systems.
Solution Approach 2:
The system applies correction values selectively based on detected fail bit patterns rather than continuously adjusting all read voltages. By performing patrol operations on selected memory regions and applying corrections only where needed, the system achieves sufficient read voltage accuracy without the full complexity of continuous comprehensive correction across all memory cells.
3Reliability
If patrol operations are performed frequently to correct read voltages, then fail bit counts reduce, but operation time increases
Solution Approach 1:
The system performs patrol operations periodically rather than continuously or before every read operation. This periodic execution of correction operations maintains data integrity by regularly updating correction values based on threshold voltage drift, while minimizing time loss by avoiding excessive patrol operations. The periodic schedule balances reliability maintenance with operational efficiency.
Data Source
AI summary
A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.