Memory Subsystem Read Voltage Adjustment via Write-to-Write Delay
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Solution Overview
Problem
In memory sub-systems, existing techniques fail to effectively manage voltage drift over time, leading to read errors and performance degradation, especially during heavy workloads and short drift times, as they do not account for varying ages of memory units and require resource-intensive read scrub operations.
Innovation Solution
The memory sub-system adjusts read voltage levels based on write-to-write delay by maintaining and updating read voltage levels for each memory unit, using a small number of bits to efficiently store and update thousands of levels, thereby compensating for temporal voltage shifts and reducing the need for read refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read scrub operations are performed to manage voltage drift, then data integrity is improved, but resource consumption and operation complexity increase
Solution Approach 1:
The system performs preliminary actions by proactively adjusting read voltage levels based on predicted drift characteristics before read errors occur. The controller modifies read voltage levels in advance based on the age of data in memory units, preventing voltage drift from causing read errors rather than correcting them after they occur.
Solution Approach 2:
The memory sub-system performs self-service by automatically managing its own voltage drift characteristics without requiring external intervention. The controller continuously monitors and adjusts read voltage levels based on internal state (data age), enabling the system to self-correct voltage drift issues without needing resource-intensive read scrub operations.
2Reliability
If read voltage levels are adjusted for each memory unit, then read error rates are reduced, but storage requirements increase
Solution Approach 1:
The system applies local quality by tailoring read voltage levels to specific memory units based on their individual characteristics and data ages. Different memory units receive different read voltage levels according to how long their data has been stored, allowing optimized read operations for each local condition rather than using a uniform approach.
Solution Approach 2:
The system changes the parameter of read voltage levels dynamically based on data age. The controller adjusts voltage levels as a function of time since the last write operation, transitioning voltage parameters to compensate for voltage drift that occurs over time in non-volatile memory units.
3Reliability
If read scrub operations are performed frequently, then voltage drift is managed, but performance degradation increases
Solution Approach 1:
The system performs preliminary voltage adjustments based on predicted drift characteristics before actual read errors occur. By proactively modifying read voltage levels according to data age, the system prevents the need for reactive read scrub operations that would degrade performance.
Solution Approach 2:
The system replaces the mechanical read scrub operation with an electrical parameter adjustment approach. Instead of physically reading and rewriting data to correct voltage drift, the system substitutes this with direct modification of read voltage levels, achieving the same voltage drift management goal with minimal performance impact.
4Device complexity
If a small number of bits are used to store read voltage levels, then device complexity is reduced, but precision of voltage representation decreases
Solution Approach 1:
The system changes the parameter representation by using a small number of bits to encode read voltage levels that correspond to discrete voltage steps. This quantized approach provides sufficient precision for voltage drift compensation while maintaining low storage complexity, as the voltage levels are represented as indexed values rather than full floating-point numbers.
Data Source
AI summary
A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.