Nonvolatile Memory Read Voltage Selection for Error Reduction
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Solution Overview
Problem
Highly integrated semiconductor storage devices face reliability issues due to scaling-down and structural changes, leading to data damage and reduced reliability, necessitating improved methods for enhancing storage device speed and reliability.
Innovation Solution
A nonvolatile memory device with a memory cell array, row decoder circuit, and page buffer circuit that applies specific read and program voltages to optimize memory cell operations, including using adjacent read voltages and verification voltages to manage bit transitions and prevent errors during read and program operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high degree of integration is implemented to reduce manufacturing cost, then manufacturing cost is reduced, but data damage occurs and reliability is lowered
Solution Approach 1:
The patent applies preliminary action by performing verification operations after program operations to detect and correct potential data damage before it affects storage reliability. The verification process checks programmed data and reprograms erroneous bits, preventing reliability degradation that would otherwise result from high-density integration effects.
2Adaptability or versatility
If scaling-down and structural changes are implemented to increase integration, then device integration is improved, but data damage occurs and reliability is lowered
Solution Approach 1:
The patent implements feedback mechanisms where verification operations provide information about programmed data quality back to the control logic. This feedback enables identification of erroneous bits and triggers reprogramming operations, creating a closed-loop system that maintains reliability despite scaling-down and structural changes required for higher integration.
3Reliability
If verification operations are performed to improve reliability, then reliability is improved, but operating time is increased
Solution Approach 1:
The patent applies partial action by performing verification operations selectively on specific word lines that require reliability checking, rather than verifying all data continuously. The control logic determines when verification is necessary based on operation type and data importance, reducing unnecessary verification time while maintaining reliability for critical operations.
Data Source
AI summary
A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a row decoder circuit connected to the memory cell array through a plurality of word lines; and a page buffer circuit connected to the memory cell array through bit lines. The row decoder circuit applies read voltages to a selected word line during a read operation. During a read operation performed with respect to each of N logical pages (N being a positive integer) of memory cells connected to the selected word line, the row decoder circuit applies a read voltage from among adjacent N read voltages to the selected word line without applying read voltages other than the adjacent N read voltages to the selected word line. The adjacent N read voltages include a second highest read voltage among the read voltages.