Memory System Read Voltage Adjustment for Fail Bit Reduction
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Solution Overview
Problem
The existing memory systems face challenges in maintaining accurate data reading due to threshold voltage shifts caused by capacitance coupling over time, leading to increased fail bits and reduced reliability, especially when the elapsed time since the last access falls within specific time periods.
Innovation Solution
A memory system that includes a controller and a NAND flash memory, where the controller issues different read command sequences based on elapsed time since the last access, adjusting the read voltage by applying specific shift amounts to optimize the read voltage for each state of the threshold voltage, thereby reducing the number of fail bits and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard read command sequence is used for reading data from the memory cell, then the read operation can be performed with simple control logic, but the number of fail bits increases due to threshold voltage shifts caused by capacitance coupling over time
Solution Approach 1:
The patent applies dynamics by making the read command sequence variable based on elapsed time. The controller dynamically selects between a first read command sequence (with adjusted read voltages) and a second read command sequence (standard voltages) depending on whether the elapsed time since last access falls within a specific time period. This resolves the contradiction by adapting the read operation to temporal conditions, improving reliability during critical time windows while maintaining simple standard operations elsewhere.
Solution Approach 2:
The patent changes the voltage parameters of the read command sequence based on elapsed time conditions. When the elapsed time is within the specific time period, the first read command sequence uses adjusted read voltages (different from standard voltages) to compensate for threshold voltage shifts. This parameter adaptation resolves the contradiction by optimizing voltage levels to counteract time-dependent degradation while keeping the system simple outside this critical time window.
2Reliability
If the read voltage is adjusted to compensate for threshold voltage shifts, then the number of fail bits is reduced, but the control complexity and power consumption increase
Solution Approach 1:
The patent segments the time domain into two regions: a specific time period where threshold voltage shifts are significant, and other time periods where standard reading suffices. By applying voltage adjustment only during the critical segmented time window, the patent reduces fail bits when necessary while minimizing unnecessary power consumption during periods when standard reading is adequate.
Solution Approach 2:
The patent applies partial action by using voltage adjustment only partially - specifically, only when the elapsed time since last access falls within the identified specific time period. This selective application of the corrective measure reduces fail bits during critical periods while avoiding excessive power consumption that would result from continuous voltage adjustment regardless of temporal conditions.
3Reliability
If different read command sequences are issued based on elapsed time, then the number of fail bits is reduced across different time periods, but the controller complexity increases
Solution Approach 1:
The patent implements dynamic control where the controller automatically selects between two read command sequences based on the elapsed time since the last access to the memory block. This time-dependent dynamic selection resolves the contradiction by introducing minimal control logic that adapts to temporal conditions, improving reliability during critical time windows while keeping the overall controller design relatively simple through automated time-based decision-making.
Data Source
AI summary
According to one embodiment, a memory system includes: a semiconductor memory including a memory cell array, the memory cell array including a memory cell, and a controller configured to issue a first read command sequence after a lapse of a first time period from access to the semiconductor memory, and issue a second read command sequence after a lapse of a second time period from access to the semiconductor memory. When the controller issues the first read command sequence, the semiconductor memory applies a first voltage and a second voltage to the memory cell. When the controller issues the second read command sequence, the semiconductor memory applies a third voltage and a fourth voltage to the memory cell.