Non-Volatile Memory Read Voltage Selection for Inner and Outer Pillars
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Solution Overview
Problem
Conventional non-volatile memory devices, such as NAND flash memory, often treat data read operations from inner and outer pillar memory cell strings uniformly, despite differences in their performance characteristics, leading to inefficiencies and increased read operation latency due to process variations and shifts in memory cell threshold voltage distributions.
Innovation Solution
The implementation of a memory device with a data input/output circuit that includes a page buffer circuit and a read voltage determination unit, which selectively connects bit lines to outer and inner memory cell strings and dynamically selects optimal read voltages based on candidate voltages for each type of memory cell string, optimizing read operations by accounting for the distinct performance characteristics of inner and outer pillar memory cell strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If uniform read voltage is applied to all memory cell strings, then device complexity is reduced, but read operation accuracy deteriorates due to process variations and threshold voltage shifts
Solution Approach 1:
The patent applies different read voltages to different regions (inner and outer pillars) of the memory cell array based on their specific performance characteristics and threshold voltage distributions. This local differentiation resolves the contradiction by tailoring the read voltage to each region's needs, improving read accuracy without requiring complete uniformity across the entire device.
Solution Approach 2:
The patent dynamically selects read voltages from multiple candidate voltages based on detected threshold voltage shifts and performance characteristics. This dynamic adjustment allows the system to adapt to process variations and maintain high read accuracy, resolving the contradiction between simple uniform voltage application and accurate region-specific voltage application.
2Measurement precision
If separate read voltages are selected for inner and outer pillar memory cell strings, then read operation accuracy is improved, but device complexity increases
Solution Approach 1:
The patent pre-determines multiple candidate read voltages and stores them for selection during read operations. This preliminary preparation of voltage options allows the system to quickly select the appropriate voltage without complex real-time calculations, reducing the actual operational complexity while maintaining high read accuracy.
Solution Approach 2:
The patent uses feedback from threshold voltage detection and performance monitoring to select the optimal read voltage from candidate voltages. This feedback mechanism enables accurate voltage selection based on actual device state, improving read accuracy while using a systematic approach that manages complexity through structured decision-making.
3Ease of operation
If uniform read operation is used for all memory cell strings, then ease of operation is maintained, but productivity decreases due to increased read-retry attempts
Solution Approach 1:
The patent segments the memory cell array into inner and outer pillar regions with different performance characteristics, and applies different read voltage strategies to each segment. This segmentation allows optimized read operations for each region, reducing the need for read-retry attempts and improving overall productivity while maintaining ease of operation through automated region identification and voltage selection.
Data Source
AI summary
A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.