3D Memory Read Pass Voltage Adjustment for Over-Programmed Cells
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Solution Overview
Problem
Semiconductor memory devices with 3D structures face read failures due to over-programmed memory cells, which disrupt the normal operation and data retrieval process, as the threshold voltages of over-programmed cells become higher than the standard read pass voltage, preventing proper current paths and leading to incorrect data reading.
Innovation Solution
A method and device that determine the target word line coupled to an over-programmed memory cell, backup data stored in that area, and apply a stepped-up read pass voltage to prevent read failures, while also invalidating and updating data addresses to ensure stable read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard read pass voltage is applied to memory cells, then normal read operations can be performed, but over-programmed memory cells cause read failures due to their higher threshold voltages
Solution Approach 1:
The patent applies different read pass voltages to different word lines based on their specific conditions. Word lines containing over-programmed memory cells receive a stepped-up read pass voltage, while other word lines receive the standard read pass voltage. This local differentiation resolves the contradiction by maintaining read operation simplicity for most cells while ensuring reliability for problematic cells.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on the state of memory cells. By detecting over-programmed cells and adjusting the read pass voltage accordingly, the system adapts to different conditions. This parameter change enables the system to maintain both simplicity and reliability by using the standard voltage when possible and the stepped-up voltage only when necessary.
2Reliability
If a stepped-up read pass voltage is applied to all memory cells, then read failures due to over-programmed cells are prevented, but the complexity of the read operation increases
Solution Approach 1:
The patent segments the memory array into different groups based on the presence of over-programmed cells. Instead of applying a stepped-up voltage to all cells uniformly, the system identifies and segments only the affected word lines, applying the stepped-up voltage selectively. This segmentation approach maintains reliability while minimizing the complexity increase to only the necessary portions of the system.
Solution Approach 2:
The patent applies the stepped-up read pass voltage partially, only to word lines that contain over-programmed memory cells, rather than to all word lines. This partial action approach ensures reliability for problematic cells while avoiding the unnecessary complexity that would result from applying the stepped-up voltage universally.
3Reliability
If data is backed up to a second memory area, then data loss from over-programmed cells is prevented, but the device complexity increases due to additional memory management
Solution Approach 1:
The patent performs preliminary actions by detecting over-programmed cells and backing up their data before read operations occur. This advance preparation ensures that even if read failures occur, the data is already preserved in a second memory area. The preliminary action approach maintains reliability while managing complexity through proactive rather than reactive measures.
Solution Approach 2:
The patent creates a copy of data from the first memory area to a second memory area for cells identified as over-programmed. This copying mechanism ensures data preservation without requiring fundamental changes to the memory architecture. The complexity increase is minimized by using a simple copy operation rather than more complex data protection mechanisms.
Data Source
AI summary
A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes determining a target word line coupled to an over-programmed memory cell, backing up data stored in memory cells coupled to the target word line in a second memory area, wherein the se second memory area is different from a first memory area where the memory cells coupled to the target word line are disposed, and applying a stepped-up read pass voltage to the target word line when a read operation is performed on a selected memory cell in a memory block coupled to the target word line, wherein the selected memory cell is different from the over-programmed memory cell. Therefore, the operation reliability of the semiconductor memory device is improved.