Memory Read Voltage Adjustment Using OVS Latch Status Bits
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Solution Overview
Problem
As semiconductor memory devices increase in capacity and reduce circuit line width, threshold voltage overlap and coupling between memory cells become significant, making it challenging to correctly read data based on ideal read voltage, especially after successful error correcting code (ECC) decoding.
Innovation Solution
A non-volatile memory device and method that estimate threshold voltage distribution using status bits during an on-chip valley search (OVS) read operation and adjust the read voltage based on these estimates, even after successful ECC decoding, to ensure accurate data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-leveling method and scaling method are used to increase capacity and reduce circuit line width, then storage capacity and integration degree are improved, but threshold voltage overlap increases and coupling between memory cells is generated
Solution Approach 1:
The patent performs preliminary actions by conducting multiple read operations at different read voltages before final data retrieval. The memory controller reads data at an initial read voltage, then performs additional reads at adjusted read voltages based on threshold voltage distribution analysis, thereby preparing compensatory measures in advance to counteract the threshold voltage overlap problem caused by multi-leveling and scaling.
Solution Approach 2:
The patent dynamically changes the read voltage parameter based on detected threshold voltage distribution characteristics. The memory controller adjusts the read voltage level according to the analyzed threshold voltage overlap and coupling effects, thereby adapting the reading process to the actual physical state of the memory cells and resolving the precision degradation caused by high-density integration.
2Quantity of substance
If the number of bits stored by cell increases, then storage capacity is improved, but overlap of threshold voltage distribution increases
Solution Approach 1:
The patent segments the reading process into multiple stages, performing separate read operations at different voltage levels. Instead of attempting to read all bits simultaneously at a single voltage, the controller divides the read operation into multiple sequential reads, each targeting specific voltage regions, thereby resolving the overlapping threshold voltage distributions that result from storing multiple bits per cell.
Solution Approach 2:
The patent implements feedback by analyzing the results of initial read operations and using this information to adjust subsequent read voltages. The memory controller monitors the detected data patterns and threshold voltage characteristics, then feeds this information back to modify the read voltage for subsequent operations, thereby compensating for the threshold voltage overlap caused by multi-level cells.
3Productivity
If circuit line width is reduced to improve integration, then device density is improved, but coupling between neighboring memory cells is generated
Solution Approach 1:
The patent applies preliminary anti-action by performing compensatory read operations that counteract the coupling effects before final data determination. The memory controller detects signs of coupling interference in initial reads and performs additional reads with adjusted voltages that compensate for the anticipated coupling effects, thereby neutralizing the harmful interference generated by reduced circuit line width.
Data Source
AI summary
A memory controller includes an error correction code (ECC) module for performing ECC decoding based on read data received from a non-volatile memory device for performing an on-chip valley search (OVS) read operation. A read voltage modification module receives status bits representing a latch that latches the read data among a plurality of latches included in the non-volatile memory device to store result values of the OVS read operation and determine whether to change a read voltage based on the status bits when the ECC decoding is successfully performed.