Memory Cell Read Voltage Offsets for Quick Charge Loss
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Solution Overview
Problem
Memory systems experience read errors due to quick charge loss (QCL) during which the threshold read voltage is mis-calibrated, leading to increased errors and inefficient read operations.
Innovation Solution
Applying a voltage offset to the threshold read voltage during the QCL duration to account for the higher charge stored in memory cells, followed by reverting to the threshold read voltage after the QCL duration to reduce errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the threshold read voltage is used for reading memory cells during quick charge loss duration, then the read operation can be performed, but read errors increase due to voltage miscalibration
Solution Approach 1:
The patent applies a dynamic voltage offset adjustment mechanism that adapts the read voltage based on the time elapsed since the program operation. During QCL duration, a first voltage offset is applied, and after QCL duration, a second voltage offset is applied. This dynamic adjustment resolves the contradiction by maintaining read accuracy (reliability) while enabling continuous read operations (productivity) without requiring voltage recalibration for each read.
Solution Approach 2:
The patent changes the voltage parameter dynamically based on the charge loss state. By transitioning from a first voltage offset during QCL to a second voltage offset after QCL, the system adapts to the changing charge characteristics of memory cells, thereby maintaining read accuracy while preserving operational continuity.
2Reliability
If voltage offset is applied during QCL duration to maintain read accuracy, then read errors are reduced, but power consumption increases
Solution Approach 1:
The patent implements periodic voltage offset adjustment based on time intervals since program operation. By applying different voltage offsets in different time periods (during QCL vs. after QCL), the system maintains read accuracy only when necessary, thereby reducing overall power consumption compared to continuously applying high voltage offsets.
Solution Approach 2:
The patent proactively applies a first voltage offset during the anticipated QCL duration to prevent read errors before they occur. This preliminary action avoids the need for error correction and subsequent voltage adjustments, thereby reducing total power consumption while maintaining reliability during the critical QCL period.
3Measurement precision
If threshold read voltage calibration is performed for plateau charge duration, then reads during plateau period are accurate, but reads during QCL duration result in errors
Solution Approach 1:
The patent applies different voltage offsets for different charge loss states: a first voltage offset specifically for QCL duration and a second voltage offset for plateau duration. This localized voltage adjustment resolves the contradiction by optimizing read accuracy for each specific charge state rather than using a single calibration voltage, thereby achieving both precision and adaptability.
Solution Approach 2:
The system dynamically switches between different voltage offset values based on the charge loss state and time elapsed since programming. This dynamic adaptation allows the read voltage to be optimally matched to the current charge state, resolving the contradiction between calibration accuracy for plateau duration and adaptability for QCL duration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces read errors and latency, decreases power consumption, and extends the life of electronic devices by optimizing read operations during charge discharge phases.
Implementation Method 1
The memory cell may store (e.g., hold, maintain) an amount of charge following the write operation
Implementation Method 2
The memory cell may discharge at a relatively high rate after the program operation (e.g., for a quick charge loss (QCL) duration) before the charge stored by the memory cell plateaus for a period
Data Source
AI summary
Methods, systems, and devices for mitigation methods for impact of quick charge loss (QCL) on read errors are described. The described techniques enable a memory system to determine a duration following a write operation during which a memory cell may experience QCL associated with discharge of the memory cell at a relatively high rate. The memory system may apply, to the memory cell, a voltage offset in addition to a threshold read voltage when performing read operations during the QCL duration, and may not apply the voltage offset when performing read operations following the QCL duration. Accordingly, the memory system may use a relatively higher read voltage for read operations performed during the QCL duration and a relatively lower read voltage for read operations following the QCL duration, which may result in relatively fewer errors.