Semiconductor Memory Read Circuit Adaptive Voltage Selection
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining accurate data reading due to drifting resistance characteristics over time, leading to potential misreading of data stored in memory cells, and existing technologies struggle to effectively extend the read window margin.
Innovation Solution
The implementation of a semiconductor memory device with a read circuit and control circuit that rereads data from memory cells using different read voltages based on the initial read data signal, specifically targeting high resistance states to ensure accurate data retrieval and extend the read window margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single read voltage is used for all memory cells, then the read circuit is simple and fast, but memory cells with drifting resistance characteristics cannot be accurately read
Solution Approach 1:
The patent implements dynamic read voltage selection where the read circuit adaptively chooses between first and second read voltages based on the resistance state of memory cells. The control circuit determines which read voltage to apply by analyzing resistance characteristics, enabling the system to dynamically adjust to drifting resistance properties and maintain accurate data reading.
Solution Approach 2:
The patent changes the read voltage parameter from a fixed single value to a selectable range of values (first read voltage and second read voltage). By varying the read voltage parameter based on detected resistance characteristics, the system can accommodate memory cells with different resistance states and drifting characteristics, thereby improving reading accuracy.
2Measurement precision
If memory cells are reread using different read voltages, then the read window margin is extended and reading accuracy is improved, but the reading time increases
Solution Approach 1:
The patent implements a feedback mechanism where the control circuit monitors the resistance characteristics of memory cells during the read operation. Based on this feedback, the control circuit determines whether a reread operation is necessary by comparing resistance values against threshold criteria. This selective feedback approach extends the read window margin only when needed, minimizing unnecessary additional read operations and time loss.
Solution Approach 2:
The patent applies partial action by performing reread operations only on memory cells that exhibit resistance characteristics indicating potential reading errors. Instead of rereading all memory cells, the control circuit selectively applies the second read voltage only to cells that require it, thereby extending the read window margin for problematic cells while avoiding unnecessary time expenditure on cells that read correctly on the first attempt.
3Reliability
If all memory cells are reread to accommodate drifting characteristics, then reading reliability is improved, but the overall system performance decreases
Solution Approach 1:
The patent applies local quality by treating different memory cells differently based on their individual resistance characteristics. Instead of applying a uniform reread strategy to all memory cells, the control circuit identifies specific cells with drifting characteristics and applies the second read voltage only to those local instances. This selective approach maintains high reading reliability for problematic cells while preserving overall system performance by avoiding unnecessary operations on normal cells.
Data Source
AI summary
An electronic device includes a semiconductor memory. The semiconductor memory may include: a memory circuit comprising a plurality of memory cells; a read circuit configured to generate a first read data signal by reading data from a read target memory cell according to a first read control signal, the read target memory cell being among the plurality of memory cells; and a control circuit configured to control the read circuit to reread the data from the read target memory cell by generating a second read control signal, the second read control signal being based on a data value of the first read data signal.